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1. 发明授权

US08633758B2 Semiconductor device having boosting circuit 失效
标题翻译：具有升压电路的半导体装置
公开(公告)号：US08633758B2
公开(公告)日：2014-01-21
申请号：US13064237
申请日：2011-03-11
申请人： Hiroki Fujisawa , Shuichi Kubouchi , Hitoshi Tanaka
发明人： Hiroki Fujisawa , Shuichi Kubouchi , Hitoshi Tanaka
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/46 , G11C5/145 , H02M1/15 , H02M3/07 , H02M2001/0045
摘要： A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit.
摘要翻译：一种半导体器件包括：升压电路，其根据外部电源电压升压升压范围内的内部电源电压;将外部电源电压与规定的基准电压进行比较的外部电压电平比较电路;以及可变电阻器电路包括连接到升压电路的输出端子的可变电阻器。可变电阻电路基于外部电压电平比较电路的比较结果来控制可变电阻器的电阻值。

2. 发明授权

US08630129B2 Semiconductor device having plural banks 失效
标题翻译：具有多个堤的半导体装置
公开(公告)号：US08630129B2
公开(公告)日：2014-01-14
申请号：US13304062
申请日：2011-11-23
申请人： Hiroki Fujisawa , Yuuji Motoyama
发明人： Hiroki Fujisawa , Yuuji Motoyama
IPC分类号： G11C7/10
CPC分类号： G11C11/4087 , G11C11/4096 , G11C11/4097
摘要： A semiconductor device is provided with a control circuit generating a plurality of first control signals indicating timings at which column switches conduct at the time of reading and a plurality of second control signals indicating timings at which the column switches conduct at the time of writing. The control circuit activates the plurality of first control signals such that timing at which the data read from each of memory cell arrays arrives at a FIFO circuit after reception of a read instruction from outside is the same in each bank and activates the plurality of second control signals such that the column switches match a timing at which write data input from outside to a first data input/output terminal arrives at the corresponding column switch.
摘要翻译：半导体器件设置有控制电路，该控制电路产生多个第一控制信号，该第一控制信号指示列开关在读取时导通的定时;以及多个第二控制信号，其指示列开关在写入时进行的定时。控制电路激活多个第一控制信号，使得在从外部接收到读指令之后从每个存储单元阵列读取的数据到达FIFO电路的定时在每个存储体中相同，并激活多个第二控制信号使得列开关匹配从外部输入到第一数据输入/输出端的写入数据到达对应的列开关的定时。

3. 发明授权

US08553489B2 Semiconductor device having point-shift type FIFO circuit 有权
标题翻译：具有点移型FIFO电路的半导体器件
公开(公告)号：US08553489B2
公开(公告)日：2013-10-08
申请号：US13317601
申请日：2011-10-24
申请人： Hiroki Fujisawa , Yuuji Motoyama
发明人： Hiroki Fujisawa , Yuuji Motoyama
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C8/18 , G11C11/408
摘要： For example, a semiconductor device includes latch circuits, whose input nodes are connected to an input selection circuit and whose output nodes are connected to an output selection circuit; and a control circuit, which controls the input selection circuit and the output selection circuit. The control circuit includes a shift register to generate an input pointer signal and a binary counter to generate an output pointer signal. The input selection circuit selects one of the latch circuits on the basis of a value of the input pointer signal. The output selection circuit selects one of the latch circuits on the basis of a value of the output pointer signal. Therefore, it is possible to prevent a hazard from occurring in the input selection circuit, as well as to reduce the number of signal lines that transmit the output pointer signal.
摘要翻译：例如，半导体器件包括锁存电路，其输入节点连接到输入选择电路，其输出节点连接到输出选择电路; 以及控制电路，其控制输入选择电路和输出选择电路。控制电路包括用于产生输入指针信号的移位寄存器和产生输出指针信号的二进制计数器。输入选择电路基于输入指针信号的值选择一个锁存电路。输出选择电路根据输出指针信号的值选择一个锁存电路。因此，可以防止在输入选择电路中发生危险，并且可以减少发送输出指针信号的信号线的数量。

4. 发明授权

US08427856B2 Semiconductor device having bit lines and local I/O lines 失效
标题翻译：具有位线和本地I / O线的半导体器件
公开(公告)号：US08427856B2
公开(公告)日：2013-04-23
申请号：US13246458
申请日：2011-09-27
申请人： Shingo Mitsubori , Hiroki Fujisawa
发明人： Shingo Mitsubori , Hiroki Fujisawa
IPC分类号： G11C5/06
CPC分类号： G11C29/025 , G11C2029/1204
摘要： The present invention efficiently decides line failure and contact failure in a semiconductor device. The semiconductor device has a plurality of bit line groups in which connection with local I/O lines is controlled by the same column selection signal line. A failure detecting circuit compares a first data group read from a first bit line group and a second data group read from a second bit line group to detect whether or not connection failure (contact failure) with the column selection signal line occurs in one of the first and second bit line groups.
摘要翻译：本发明有效地确定半导体器件中的线路故障和接触故障。半导体器件具有多个位线组，其中与本地I / O线的连接由相同的列选择信号线控制。故障检测电路比较从第一位线组读取的第一数据组和从第二位线组读取的第二数据组，以检测与列选择信号线的连接故障（接触故障）是否发生在第一和第二位线组。

5. 发明授权

US08422326B2 Semiconductor device having sense amplifier 有权
标题翻译：具有读出放大器的半导体器件
公开(公告)号：US08422326B2
公开(公告)日：2013-04-16
申请号：US13304040
申请日：2011-11-23
申请人： Hiroki Fujisawa , Ryuuji Takishita
发明人： Hiroki Fujisawa , Ryuuji Takishita
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , G11C7/065
摘要： For example, four driver transistors are arranged in wells so as to adjoin both sides of each of two element isolation regions. Two pairs of cross-coupled sense transistors are arranged in the wells at positions farther from the element isolation regions than the driver transistors are. Such an arrangement provides more than a certain distance between the sense transistors and the respective corresponding element isolation regions. This reduces the effect of a phenomenon that threshold of a transistor varies according to a distance from an element isolation region. As a result, it is possible to exactly match the characteristics of each pair of cross-coupled transistors.
摘要翻译：例如，四个驱动晶体管布置在阱中，以便邻接两个元件隔离区域中的每一个的两侧。两个交叉耦合的检测晶体管布置在阱中，比驱动晶体管更远离元件隔离区的位置。这种布置在感测晶体管和相应的对应元件隔离区域之间提供超过一定距离。这降低了晶体管的阈值根据与元件隔离区域的距离而变化的现象的影响。结果，可以精确地匹配每对交叉耦合晶体管的特性。

6. 发明授权

US08274843B2 Semiconductor device having nonvolatile memory element and data processing system including the same 有权
公开(公告)号：US08274843B2
公开(公告)日：2012-09-25
申请号：US12695784
申请日：2010-01-28
申请人： Yoshio Mizukane , Hiroki Fujisawa
发明人： Yoshio Mizukane , Hiroki Fujisawa
IPC分类号： G11C7/10 , G11C17/16 , G11C7/00
CPC分类号： G11C11/4072 , G11C7/1045 , G11C7/1066 , G11C7/20
摘要： A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation.

7. 发明申请

US20120120753A1 Semiconductor device having point-shift type FIFO circuit 有权
标题翻译：具有点移型FIFO电路的半导体器件
公开(公告)号：US20120120753A1
公开(公告)日：2012-05-17
申请号：US13317601
申请日：2011-10-24
申请人： Hiroki Fujisawa , Yuuji Motoyama
发明人： Hiroki Fujisawa , Yuuji Motoyama
IPC分类号： G11C8/06 , G11C8/10
CPC分类号： G11C11/4076 , G11C8/18 , G11C11/408
摘要： For example, a semiconductor device includes latch circuits, whose input nodes are connected to an input selection circuit and whose output nodes are connected to an output selection circuit; and a control circuit, which controls the input selection circuit and the output selection circuit. The control circuit includes a shift register to generate an input pointer signal and a binary counter to generate an output pointer signal. The input selection circuit selects one of the latch circuits on the basis of a value of the input pointer signal. The output selection circuit selects one of the latch circuits on the basis of a value of the output pointer signal. Therefore, it is possible to prevent a hazard from occurring in the input selection circuit, as well as to reduce the number of signal lines that transmit the output pointer signal.
摘要翻译：例如，半导体器件包括锁存电路，其输入节点连接到输入选择电路，其输出节点连接到输出选择电路; 以及控制电路，其控制输入选择电路和输出选择电路。控制电路包括用于产生输入指针信号的移位寄存器和产生输出指针信号的二进制计数器。输入选择电路基于输入指针信号的值选择一个锁存电路。输出选择电路根据输出指针信号的值选择一个锁存电路。因此，可以防止在输入选择电路中发生危险，并且可以减少发送输出指针信号的信号线的数量。

8. 发明申请

US20120112540A1 SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：半导体芯片和半导体器件，包括它们
公开(公告)号：US20120112540A1
公开(公告)日：2012-05-10
申请号：US13278755
申请日：2011-10-21
申请人： Hiromasa TAKEDA , Hiroki Fujisawa
发明人： Hiromasa TAKEDA , Hiroki Fujisawa
IPC分类号： H02J1/00
CPC分类号： H01L24/14 , G11C7/1057 , H01L23/49838 , H01L23/5286 , H01L2224/1412 , H01L2224/16225 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/15311 , Y10T307/305 , Y10T307/50 , Y10T307/696 , Y10T307/707 , H01L2924/00
摘要： A semiconductor chip includes: a data output buffer that outputs a data signal; a first power-supply pad that supplies a first power-supply potential to the data output buffer; a power-supply wiring that is connected to the first power-supply pad; a strobe output buffer that outputs a strobe signal; and a second power-supply pad that supplies a second power-supply potential to the strobe output buffer. The power-supply wiring and the second power-supply pad are electrically independent of each other. Therefore, the power-supply noise associated with the switching of the data output buffer does not spread to the strobe output buffer. Thus, it is possible to improve the quality of the strobe signal.
摘要翻译：半导体芯片包括：输出数据信号的数据输出缓冲器; 第一电源焊盘，其向所述数据输出缓冲器提供第一电源电位; 连接到所述第一电源焊盘的电源配线; 输出选通信号的选通输出缓冲器; 以及向所述选通输出缓冲器提供第二电源电位的第二电源焊盘。电源布线和第二电源垫彼此电独立。因此，与数据输出缓冲器的切换相关联的电源噪声不会扩展到选通输出缓冲器。因此，可以提高选通信号的质量。

9. 发明授权

US08144524B2 Semiconductor device and semiconductor package including the same 有权
标题翻译：半导体器件和包括其的半导体封装
公开(公告)号：US08144524B2
公开(公告)日：2012-03-27
申请号：US12923254
申请日：2010-09-10
申请人： Yoshio Mizukane , Hiroki Fujisawa
发明人： Yoshio Mizukane , Hiroki Fujisawa
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C5/06 , G11C7/1051 , G11C7/1057 , G11C11/4093 , G11C2207/105 , G11C2207/2254
摘要： To include a plurality of pad groups each including a first data I/O pad, a first power supply pad, a second data I/O pad, and a second power supply pad arranged in order in an X direction. The first data I/O pad is connected to a first data I/O buffer, and the second data I/O pad is connected to a second data I/O buffer. The first power supply pad supplies a first power supply potential to the first and second data I/O buffers, and the second power supply pad supplies a second power supply potential to the first and second data I/O buffers. The first data I/O pad included in each of the pad groups is adjacent to the second power supply pad included in other pad group or any one of a plurality of power supply pads not included in any one of the pad groups.
摘要翻译：包括多个焊盘组，每个焊盘组包括在X方向上顺序布置的第一数据I / O焊盘，第一电源焊盘，第二数据I / O焊盘和第二电源焊盘。第一数据I / O焊盘连接到第一数据I / O缓冲器，第二数据I / O焊盘连接到第二数据I / O缓冲器。第一电源焊盘为第一和第二数据I / O缓冲器提供第一电源电位，第二电源焊盘向第一和第二数据I / O缓冲器提供第二电源电位。包括在每个焊盘组中的第一数据I / O焊盘与包括在其它焊盘组中的第二电源焊盘或不包括在任何一个焊盘组中的多个电源焊盘中的任何一个电源焊盘相邻。

10. 发明授权

US07994812B2 Calibration circuit, semiconductor device including the same, and data processing system 有权
标题翻译：校准电路，包括相同的半导体器件和数据处理系统
公开(公告)号：US07994812B2
公开(公告)日：2011-08-09
申请号：US12654253
申请日：2009-12-15
申请人： Fumiyuki Osanai , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H03K17/16
CPC分类号： H03K19/0005
摘要： A semiconductor device adjusting an impedance level of an output buffer, includes a replica buffer circuit including a circuit configuration substantially identical to the output buffer, a counter circuit changing an impedance code to vary an impedance level of the replica buffer, a latch circuit temporarily holding the impedance code in response to a control signal, and an end-determining circuit producing the control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level.
摘要翻译：调整输出缓冲器的阻抗水平的半导体器件包括复制缓冲电路，其包括与输出缓冲器基本相同的电路配置，计数器电路改变阻抗代码以改变副本缓冲器的阻抗电平;锁存电路暂时保持响应于控制信号的阻抗代码，以及响应于从校准命令的发布而经过预定时间段而产生控制信号的终止确定电路，而不管复制缓冲器尚未达到期望的事实阻抗水平。

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