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1. 发明申请

US20210132902A1 FLOATING POINT TO FIXED POINT CONVERSION 有权
公开(公告)号：US20210132902A1
公开(公告)日：2021-05-06
申请号：US17141284
申请日：2021-01-05
申请人： Imagination Technologies Limited
发明人： Kenneth Rovers
IPC分类号： G06F5/01 , H03M7/24 , G06F7/48
摘要： A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew−1),bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

2. 发明授权

US10884702B2 Floating point to fixed point conversion 有权
公开(公告)号：US10884702B2
公开(公告)日：2021-01-05
申请号：US16876402
申请日：2020-05-18
申请人： Imagination Technologies Limited
发明人： Kenneth Rovers
IPC分类号： G06F5/01 , G06F7/48 , H03M7/24
摘要： A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min {(ew−1), bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

3. 发明申请

US20200142668A1 Floating Point to Fixed Point Conversion 审中-公开
公开(公告)号：US20200142668A1
公开(公告)日：2020-05-07
申请号：US16734317
申请日：2020-01-04
申请人： Imagination Technologies Limited
发明人： Kenneth Rovers
IPC分类号： G06F5/01 , G06F7/48 , H03M7/24
摘要： A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew−1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew −1), bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

4. 发明授权

US10558428B2 Floating point to fixed point conversion 有权
公开(公告)号：US10558428B2
公开(公告)日：2020-02-11
申请号：US15935313
申请日：2018-03-26
申请人： Imagination Technologies Limited
发明人： Kenneth Rovers
IPC分类号： G06F5/01 , H03M7/24 , G06F7/48
摘要： A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a first shifter operable to receive a first significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a first output, wherein min{(ew−1), bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number; an inverting unit configured to invert the bit values of the exponent; a second shifter coupled to the inverting unit configured to receive a second significand input comprising a contiguous set of the most significant bits of the significand and configured to right-shift the input by a number of bits equal to the value represented by the p least significant bits of the inverted exponent to generate a second output, wherein min{(ew−1), bitwidth(fw)}≤p≤(ew−1); and a multiplexer coupled to the first and second shifters and configured to: receive a first input comprising a contiguous set of bits of the first output and a second input comprising a contiguous set of bits of the second output; and output the first input if the most significant bit of the exponent is equal to one; and output the second input if the most significant bit of the exponent is equal to zero.

5. 发明授权

US11544892B2 Decoder unit for texture decompression 有权
公开(公告)号：US11544892B2
公开(公告)日：2023-01-03
申请号：US17342485
申请日：2021-06-08
申请人： Imagination Technologies Limited
发明人： Yoong Chert Foo , Kenneth Rovers
IPC分类号： G06T15/04 , G06T9/00 , H04N19/436 , H04N19/44 , G06T11/00
摘要： A decoder unit is configured to decode a plurality of texels in accordance with a texel request, the plurality of texels being encoded across one or more blocks of encoded texture data each encoding a block of texels, and includes a first set of one or more decoders, each of the first set of decoders being configured to decode n texels from a single received block of encoded texture data; a second set of or more decoders, each of the second set of decoders being configured to decode p texels from a single received block of encoded texture data, where p

6. 发明申请

US20210358080A1 ASTC Interpolation 有权
公开(公告)号：US20210358080A1
公开(公告)日：2021-11-18
申请号：US17390623
申请日：2021-07-30
申请人： Imagination Technologies Limited
发明人： Kenneth Rovers
IPC分类号： G06T3/40 , G06T9/00 , G06T15/04
摘要： A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) colour endpoint values C0 and C1 respectively, the colour endpoint values C0 and C1 being low-dynamic range (LDR) or high dynamic range (HDR) values, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation: (1) P=└(C2 >2 when the colour endpoint values are HDR values.

7. 发明申请

US20210184693A1 FLOATING POINT TO FIXED POINT CONVERSION USING EXPONENT OFFSET 有权
公开(公告)号：US20210184693A1
公开(公告)日：2021-06-17
申请号：US17139221
申请日：2020-12-31
申请人： Imagination Technologies Limited
发明人： Kenneth Rovers
IPC分类号： H03M7/24 , G06F5/01 , G06F7/483 , G06F7/499
摘要： A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes an offset unit configured to offset the exponent of the floating point number by an offset value equal to (iw−/−sy) to generate a shift value sv of sw bits given by sv=(B−E)+(iw−1−sy), the offset value being equal to a maximum amount by which the significand can be left-shifted before overflow occurs in the fixed point format; a right-shifter operable to receive a significand input comprising a formatted set of bits derived from the significand, the shifter being configured to right-shift the input by a number of bits equal to the value represented by k least significant bits of the shift value to generate an output result, where bitwidth[min(2ew-1−1, iw−1−sy)+min(2ew-1−2, fw)]≤k≤sw, where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number.

8. 发明授权

US10691411B2 Floating point to fixed point conversion 有权
公开(公告)号：US10691411B2
公开(公告)日：2020-06-23
申请号：US16734317
申请日：2020-01-04
申请人： Imagination Technologies Limited
发明人： Kenneth Rovers
IPC分类号： G06F5/01 , H03M7/24 , G06F7/48
摘要： A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew−1), bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

9. 发明申请

US20230055989A1 ANISOTROPIC TEXTURE FILTERING BY COMBINING RESULTS OF ISOTROPIC FILTERING AT A PLURALITY OF SAMPLING POINTS WITH A GAUSSIAN FILTER 有权
公开(公告)号：US20230055989A1
公开(公告)日：2023-02-23
申请号：US17874019
申请日：2022-07-26
申请人： Imagination Technologies Limited
发明人： Rostam King , Kenneth Rovers
IPC分类号： G06T15/04 , G06T15/50 , G06T7/60
摘要： A method of performing anisotropic texture filtering includes generating one or more parameters describing an elliptical footprint in texture space; performing isotropic filtering at each of a plurality of sampling points along a major axis of the elliptical footprint, wherein a spacing between adjacent sampling points of the plurality of sampling points is proportional to √{square root over (1−η−2)} units, wherein η is a ratio of a major radius of an ellipse to be sampled and a minor radius of the ellipse to be sampled, wherein the ellipse to be sampled is based on the elliptical footprint; and combining results of the isotropic filtering at the plurality of sampling points with a Gaussian filter to generate at least a portion of a filter result.

10. 发明授权

US11043020B2 Decoder unit for texture decompression 有权
公开(公告)号：US11043020B2
公开(公告)日：2021-06-22
申请号：US16806178
申请日：2020-03-02
申请人： Imagination Technologies Limited
发明人： Yoong Chert Foo , Kenneth Rovers
IPC分类号： G06T15/04 , G06T9/00 , H04N19/436 , H04N19/44 , G06T11/00
摘要： A decoder unit is configured to decode a plurality of texels in accordance with a texel request, the plurality of texels being encoded across one or more blocks of encoded texture data each encoding a block of texels, and includes a first set of one or more decoders, each of the first set of decoders being configured to decode n texels from a single received block of encoded texture data; a second set of or more decoders, each of the second set of decoders being configured to decode p texels from a single received block of encoded texture data, where p

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