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1. 发明授权

US07467277B2 Memory controller operating in a system with a variable system clock 有权
标题翻译：内存控制器在具有可变系统时钟的系统中运行
公开(公告)号：US07467277B2
公开(公告)日：2008-12-16
申请号：US11348879
申请日：2006-02-07
申请人： Melissa Ann Barnum , Mark David Bellows , Paul Allen Ganfield , Lonny Lambrecht , Tolga Ozguner
发明人： Melissa Ann Barnum , Mark David Bellows , Paul Allen Ganfield , Lonny Lambrecht , Tolga Ozguner
IPC分类号： G06F13/14
CPC分类号： G11C8/18 , G06F13/1642 , G06F13/1689 , Y02D10/14
摘要： The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.
摘要翻译：本发明一般涉及在包含可变系统时钟的系统中操作的存储器控制器。存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。可以提供异步缓冲器以跨可变和恒定时钟域传输数据。为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

2. 发明授权

US07676639B2 Separate handling of read and write of read-modify-write 失效
标题翻译：读写修改写的单独处理
公开(公告)号：US07676639B2
公开(公告)日：2010-03-09
申请号：US12034681
申请日：2008-02-21
申请人： Melissa Ann Barnum , Paul Allen Ganfield , Lonny Lambrecht
发明人： Melissa Ann Barnum , Paul Allen Ganfield , Lonny Lambrecht
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834
摘要： Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.
摘要翻译：提供了在XDR™存储系统中单独处理读写修改写命令的读写操作。本发明允许系统在RMW的读取和写入之间发出其他命令。这确保从读取到写入的数据流时间不是一个惩罚。使用RMW缓冲器来存储读取的数据，并且使用写入缓冲器来存储写入数据。使用MUX来合并读取数据和写入数据，并通过XIO将合并的数据发送到目标DRAM。 RMW缓冲区也可用于擦除命令。

3. 发明授权

US07761682B2 Memory controller operating in a system with a variable system clock 失效
标题翻译：内存控制器在具有可变系统时钟的系统中运行
公开(公告)号：US07761682B2
公开(公告)日：2010-07-20
申请号：US12191195
申请日：2008-08-13
申请人： Melissa Ann Barnum , Mark David Bellows , Paul Allen Ganfield , Lonny Lambrecht , Tolga Ozguner
发明人： Melissa Ann Barnum , Mark David Bellows , Paul Allen Ganfield , Lonny Lambrecht , Tolga Ozguner
IPC分类号： G06F13/14 , G06F13/36
CPC分类号： G11C8/18 , G06F13/1642 , G06F13/1689 , Y02D10/14
摘要： The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.
摘要翻译：本发明一般涉及在包含可变系统时钟的系统中操作的存储器控制器。存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。可以提供异步缓冲器以跨可变和恒定时钟域传输数据。为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

4. 发明授权

US07716430B2 Separate handling of read and write of read-modify-write 失效
公开(公告)号：US07716430B2
公开(公告)日：2010-05-11
申请号：US12033910
申请日：2008-02-20
申请人： Melissa Ann Barnum , Paul Allen Ganfield , Lonny Lambrecht
发明人： Melissa Ann Barnum , Paul Allen Ganfield , Lonny Lambrecht
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834
摘要： Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

5. 发明申请

US20080307184A1 MEMORY CONTROLLER OPERATING IN A SYSTEM WITH A VARIABLE SYSTEM CLOCK 失效
标题翻译：在具有可变系统时钟的系统中操作的存储器控制器
公开(公告)号：US20080307184A1
公开(公告)日：2008-12-11
申请号：US12191195
申请日：2008-08-13
申请人： Melissa Ann Barnum , Mark David Bellows , Paul Allen Ganfield , Lonny Lambrecht , Tolga Ozguner
发明人： Melissa Ann Barnum , Mark David Bellows , Paul Allen Ganfield , Lonny Lambrecht , Tolga Ozguner
IPC分类号： G06F12/00
CPC分类号： G11C8/18 , G06F13/1642 , G06F13/1689 , Y02D10/14
摘要： The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.
摘要翻译：本发明一般涉及在包含可变系统时钟的系统中操作的存储器控制器。存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。可以提供异步缓冲器以跨可变和恒定时钟域传输数据。为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

6. 发明授权

US07363442B2 Separate handling of read and write of read-modify-write 失效
标题翻译：读写修改写的单独处理
公开(公告)号：US07363442B2
公开(公告)日：2008-04-22
申请号：US10988314
申请日：2004-11-12
申请人： Melissa Ann Barnum , Paul Allen Ganfield , Lonny Lambrecht
发明人： Melissa Ann Barnum , Paul Allen Ganfield , Lonny Lambrecht
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834
摘要： A method, an apparatus, and a computer program are provided for the separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.
摘要翻译：提供了一种方法，装置和计算机程序，用于在XDR（TM）存储器系统中单独处理读取 - 修改 - 写入命令的读取和写入操作。本发明允许系统在RMW的读取和写入之间发出其他命令。这确保从读取到写入的数据流时间不是一个惩罚。使用RMW缓冲器来存储读取的数据，并且使用写入缓冲器来存储写入数据。使用MUX来合并读取数据和写入数据，并通过XIO将合并的数据发送到目标DRAM。 RMW缓冲区也可用于擦除命令。

7. 发明申请

US20080148108A1 Separate Handling of Read and Write of Read-Modify-Write 失效
标题翻译：读/写读写的分离处理
公开(公告)号：US20080148108A1
公开(公告)日：2008-06-19
申请号：US12033910
申请日：2008-02-20
申请人： Melissa A. Barnum , Paul Allen Ganfield , Lonny Lambrecht
发明人： Melissa A. Barnum , Paul Allen Ganfield , Lonny Lambrecht
IPC分类号： G06F12/00 , G06F11/07
CPC分类号： G06F13/1673 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834
摘要： Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.
摘要翻译：提供了在XDR（TM）存储器系统中单独处理读取 - 修改 - 写入命令的读取和写入操作。本发明允许系统在RMW的读取和写入之间发出其他命令。这确保从读取到写入的数据流时间不是一个惩罚。使用RMW缓冲器来存储读取的数据，并且使用写入缓冲器来存储写入数据。使用MUX来合并读取数据和写入数据，并通过XIO将合并的数据发送到目标DRAM。 RMW缓冲区也可用于擦除命令。

8. 发明授权

US07266650B2 Method, apparatus, and computer program product for implementing enhanced circular queue using loop counts 失效
标题翻译：用于使用循环计数实现增强型循环队列的方法，装置和计算机程序产品
公开(公告)号：US07266650B2
公开(公告)日：2007-09-04
申请号：US10988232
申请日：2004-11-12
申请人： Paul Allen Ganfield , Lonny Lambrecht
发明人： Paul Allen Ganfield , Lonny Lambrecht
IPC分类号： G06F12/00
CPC分类号： G06F17/30958
摘要： A method, apparatus, and computer program product are provided for implementing an enhanced circular queue using loop counts for command processing. A circular queue includes a plurality of entries for storing commands. As command entries are added to the queue at the head of the queue, a head loop count is stored with each command entry. A head pointer is updated to the head of the queue. When the head pointer wraps from a last queue entry to a first queue entry, the head loop count is incremented. A tail pointer points to an oldest command entry, and is updated when the oldest command entry is executed. When the tail pointer advances and wraps from a last queue entry to a first queue entry, the tail pointer loop count is incremented.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于使用用于命令处理的循环计数来实现增强的循环队列。循环队列包括用于存储命令的多个条目。由于命令条目被添加到队列头部的队列中，所以每个命令条目都存储头循环计数。头指针被更新到队列的头部。当头指针从最后一个队列条目包装到第一个队列条目时，头循环计数递增。尾指针指向最旧的命令条目，并在执行最旧的命令条目时更新。当尾部指针从最后一个队列条目前进到第一个队列条目时，尾部指针循环计数递增。

9. 发明授权

US07321950B2 Method and apparatus for managing write-to-read turnarounds in an early read after write memory system 有权
标题翻译：用于在写入存储器系统之后的早期读取中管理写入读取周转的方法和装置
公开(公告)号：US07321950B2
公开(公告)日：2008-01-22
申请号：US11050021
申请日：2005-02-03
申请人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F13/1647
摘要： A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.
摘要翻译：提出了一种用于在写入存储器系统之后的早期读取中管理写入到读取周转的方法和装置。存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信号一个奇怪的DRAM银行。

10. 发明授权

US07487318B2 Managing write-to-read turnarounds in an early read after write memory system 有权
标题翻译：在写入内存系统之后的早期读取中管理写入阅读的周转时间
公开(公告)号：US07487318B2
公开(公告)日：2009-02-03
申请号：US11851468
申请日：2007-09-07
申请人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/161 , G06F13/1647
摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.
摘要翻译：介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信号一个奇怪的DRAM银行。

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