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1. 发明授权

US09337952B2 Embedded resilient buffer 有权
标题翻译：嵌入式弹性缓冲区
公开(公告)号：US09337952B2
公开(公告)日：2016-05-10
申请号：US13867968
申请日：2013-04-22
申请人： Somnath Paul , Sriram R. Vangal
发明人： Somnath Paul , Sriram R. Vangal
IPC分类号： H04L1/00 , H03K19/00 , G06F11/26 , G11C29/00 , G11C29/02 , G06F13/16 , H04L12/70
CPC分类号： G06F11/0787 , G06F5/065 , G06F11/0757 , G06F11/0772 , G06F11/1407 , G06F11/1645 , G06F11/26 , G06F13/1673 , G06F13/1689 , G06F2205/067 , G11C29/003 , G11C29/023 , G11C29/028 , H03K19/00 , H04L1/00 , H04L2012/5681 , Y02D10/14
摘要： Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.
摘要翻译：描述了一种装置，包括：第一顺序单元; 与第一顺序单元并联耦合的第一队列，使得第一队列和第一顺序单元接收第一输入，用于对第一输入进行双倍采样的第一序列; 比较单元，用于接收来自第一顺序单元的输出; 以及由前一周期的写指针控制的第一选择单元，所述第一选择单元接收所述第一队列的每个存储单元的输出，其中所述第一选择单元生成用于由所述第一比较单元进行比较的输出。

2. 发明申请

US20140095953A1 Techniques for Resilient Communication 有权
标题翻译：弹性通信技术
公开(公告)号：US20140095953A1
公开(公告)日：2014-04-03
申请号：US13631937
申请日：2012-09-29
申请人： Somnath Paul , Sriram R. Vangal , Michael D. Abbott , Eugene M. Kishinevsky
发明人： Somnath Paul , Sriram R. Vangal , Michael D. Abbott , Eugene M. Kishinevsky
IPC分类号： G06F11/14
CPC分类号： G06F11/1443 , H04L1/20 , H04L1/242
摘要： Techniques for resilient communication. A data path stores data to be transmitted over a link to a receiving node. An output stage is coupled between the data path and the link. The output stage includes double sampling mechanisms to preserve a copy of data transmitted over the link to the receiving node. Error detection circuitry is coupled with the output stage to detect transient timing errors in the data path or output stage. The error detection circuitry causes the output stage to send the copy of the data transmitted over the link in response to detecting an error.
摘要翻译：弹性沟通技巧。数据路径存储要通过链接发送到接收节点的数据。输出级耦合在数据路径和链路之间。输出级包括双重采样机制，以保留通过链路传送到接收节点的数据副本。错误检测电路与输出级耦合以检测数据通路或输出级中的瞬态定时误差。响应于检测到错误，错误检测电路使得输出级发送通过链路发送的数据的副本。

3. 发明申请

US20140317458A1 EMBEDDED RESILIENT BUFFER 有权
标题翻译：嵌入式电阻缓冲器
公开(公告)号：US20140317458A1
公开(公告)日：2014-10-23
申请号：US13867968
申请日：2013-04-22
申请人： Somnath Paul , Sriram R. Vangal
发明人： Somnath Paul , Sriram R. Vangal
IPC分类号： G06F11/07
CPC分类号： G06F11/0787 , G06F5/065 , G06F11/0757 , G06F11/0772 , G06F11/1407 , G06F11/1645 , G06F11/26 , G06F13/1673 , G06F13/1689 , G06F2205/067 , G11C29/003 , G11C29/023 , G11C29/028 , H03K19/00 , H04L1/00 , H04L2012/5681 , Y02D10/14
摘要： Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.
摘要翻译：描述了一种装置，包括：第一顺序单元; 与第一顺序单元并联耦合的第一队列，使得第一队列和第一顺序单元接收第一输入，用于对第一输入进行双倍采样的第一序列; 比较单元，用于接收来自第一顺序单元的输出; 以及由前一周期的写指针控制的第一选择单元，所述第一选择单元接收所述第一队列的每个存储单元的输出，其中所述第一选择单元生成用于由所述第一比较单元进行比较的输出。

4. 发明申请

US20160232051A1 EMBEDDED RESILIENT BUFFER 审中-公开
标题翻译：嵌入式电阻缓冲器
公开(公告)号：US20160232051A1
公开(公告)日：2016-08-11
申请号：US15132027
申请日：2016-04-18
申请人： Somnath Paul , Sriram R. Vangal
发明人： Somnath Paul , Sriram R. Vangal
IPC分类号： G06F11/07 , G06F13/16 , G06F5/06 , G06F11/16
CPC分类号： G06F11/0787 , G06F5/065 , G06F11/0757 , G06F11/0772 , G06F11/1407 , G06F11/1645 , G06F11/26 , G06F13/1673 , G06F13/1689 , G06F2205/067 , G11C29/003 , G11C29/023 , G11C29/028 , H03K19/00 , H04L1/00 , H04L2012/5681 , Y02D10/14
摘要： Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.
摘要翻译：描述了一种装置，包括：第一顺序单元; 与第一顺序单元并联耦合的第一队列，使得第一队列和第一顺序单元接收第一输入，用于对第一输入进行双倍采样的第一序列; 比较单元，用于接收来自第一顺序单元的输出; 以及由前一周期的写指针控制的第一选择单元，所述第一选择单元接收所述第一队列的每个存储单元的输出，其中所述第一选择单元生成用于由所述第一比较单元进行比较的输出。

5. 发明申请

US20220012563A1 METHODS AND APPARATUS FOR HIGH THROUGHPUT COMPRESSION OF NEURAL NETWORK WEIGHTS 有权
公开(公告)号：US20220012563A1
公开(公告)日：2022-01-13
申请号：US17484226
申请日：2021-09-24
申请人： Alejandro Castro Gonzalez , Praveen Nair , Somnath Paul , Sudheendra Kadri , Palanivel Guruvareddiar , Aaron Gubrud , Vinodh Gopal
发明人： Alejandro Castro Gonzalez , Praveen Nair , Somnath Paul , Sudheendra Kadri , Palanivel Guruvareddiar , Aaron Gubrud , Vinodh Gopal
IPC分类号： G06N3/04
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed for high throughput compression of neural network weights. An example apparatus includes at least one memory, instructions in the apparatus and processor circuitry to execute the instructions to determine sizes of data lanes in a partition of neural network weights, determine a slice size based on a size difference between a first data lane and a second data lane of the data lanes in the partition, the first data lane including first data, the second data lane including second data, the second data of a smaller size than the first data, cut a portion of the first data from the first data lane based on the slice size, and append the portion of the first data to the second data lane.

6. 发明授权

US07138930B1 Multiple byte data path encoding/decoding device and method 有权
标题翻译：多字节数据路径编码/解码装置及方法
公开(公告)号：US07138930B1
公开(公告)日：2006-11-21
申请号：US10937138
申请日：2004-09-09
申请人： Somnath Paul , Hamid Khodabandehlou
发明人： Somnath Paul , Hamid Khodabandehlou
IPC分类号： H03M7/00
CPC分类号： H03M5/145 , H04L25/14 , H04L25/4906
摘要： Systems and methods for performing encoding and/or decoding can include an input data path that receives multiple input data values having an order (significance) with respect to one another. Each input data value can be applied to multiple compute paths (106-1 to 106-N), each of which can precompute multiple output values based on a different predetermined disparity value. Multiplexers (114-1 to 114-N) can output one precomputed output value according to a disparity value corresponding to a previous input data value in the order.
摘要翻译：用于执行编码和/或解码的系统和方法可以包括输入数据路径，其接收具有相对于彼此的顺序（重要性）的多个输入数据值。每个输入数据值可以应用于多个计算路径（106-1至106-N），每个计算路径可以基于不同的预定差异值预先计算多个输出值。多路复用器（114-1至114-N）可以根据与先前输入数据值相对应的视差值输出一个预计算的输出值。

7. 发明授权

US06925506B1 Architecture for implementing virtual multiqueue fifos 失效
标题翻译：用于实现虚拟多队列fifos的架构
公开(公告)号：US06925506B1
公开(公告)日：2005-08-02
申请号：US09676704
申请日：2000-09-29
申请人： S. Babar Raza , Somnath Paul
发明人： S. Babar Raza , Somnath Paul
IPC分类号： G06F5/06 , G06F12/00 , G06F13/00
CPC分类号： G06F5/065 , G06F2205/066
摘要： A circuit configured to provide a storage device comprising one or more virtual multiqueue FIFOs. The circuit is generally configured to operate at a preferred clock speed of a plurality of clock speeds.
摘要翻译：一种被配置为提供包括一个或多个虚拟多队列FIFO的存储设备的电路。电路通常被配置为以多个时钟速度的优选时钟速度工作。

8. 发明授权

US07016349B1 Logic for generating multicast/unicast address (es) 有权
标题翻译：用于生成多播/单播地址的逻辑
公开(公告)号：US07016349B1
公开(公告)日：2006-03-21
申请号：US09676706
申请日：2000-09-29
申请人： S. Babar Raza , Somnath Paul
发明人： S. Babar Raza , Somnath Paul
IPC分类号： H04L12/56 , G06F12/00
CPC分类号： H04L49/901 , H04L49/90
摘要： An apparatus configured to extract in-band information or skip extraction of the in-band information and perform a look ahead operation. The apparatus may be configured to switch between the extraction and the skipping of the extraction.
摘要翻译：一种被配置为提取带内信息或者跳过带内信息的提取并执行预览操作的装置。该装置可以被配置为在提取和提取的跳过之间切换。

9. 发明授权

US06704863B1 Low-latency DMA handling in pipelined processors 有权
标题翻译：流水线处理器中的低延迟DMA处理
公开(公告)号：US06704863B1
公开(公告)日：2004-03-09
申请号：US09594219
申请日：2000-06-14
申请人： Somnath Paul , Gregory H. Efland
发明人： Somnath Paul , Gregory H. Efland
IPC分类号： G06F938
CPC分类号： G06F9/3861 , G06F9/3802 , G06F9/3867
摘要： A method, system and processor are provided for minimizing latency and loss of processor bandwidth in a pipelined processor when responding to an interrupt. The method advantageously avoids emptying and refilling the processor's instruction pipeline in order to service an interrupt request. Instead, a short sequence of instructions comprising the interrupt response is inserted into the pipeline. Normal pipeline operation stalls while the inserted instructions execute, but since flow is not disrupted the loss in bandwidth is not as great as if the pipeline were flushed. Furthermore, direct insertion of the instructions into the pipeline avoids the need for the processor to save its context and branch to an interrupt service routine in memory; this results in much faster response in servicing the interrupt, thereby reducing latency. In the preferred embodiment, the method applies to a pipelined processor having a RISC (Reduced Instruction Set Computer) architecture, which receives interrupt requests from one or more DMA memory controllers. The instructions inserted into the pipeline compute block address information for a DMA transfer. A system and processor implementing the method are disclosed, based on an enhancement of a conventional RISC processor design, and making use of registers and other existing logic resources within the processor. It is shown that the enhanced processor can respond to DMA interrupts with shorter latency and a smaller reduction in processor bandwidth than if conventional interrupt handling were used.
摘要翻译：提供了一种方法，系统和处理器，用于在响应中断时最小化流水线处理器中的处理器带宽的延迟和丢失。该方法有利地避免了排空和重新填充处理器的指令流水线以便服务于中断请求。相反，将包含中断响应的简短指令序列插入流水线。正常的流水线操作在插入的指令执行时停止，但是由于流量不会中断，带宽的损失不如管道被冲洗的那么大。此外，将指令直接插入到管线中避免了处理器将其上下文和分支保存到存储器中的中断服务程序的需要; 这导致在服务中断时响应更快，从而减少了延迟。在优选实施例中，该方法适用于具有从一个或多个DMA存储器控制器接收中断请求的RISC（精简指令集计算机）架构的流水线处理器。插入流水线的指令可计算DMA传输的块地址信息。基于常规RISC处理器设计的增强以及利用处理器内的寄存器和其他现有逻辑资源，公开了实现该方法的系统和处理器。显示出增强型处理器可以以较短的延迟响应DMA中断，并且比使用常规中断处理更小的处理器带宽减少。

10. 发明授权

US06578118B1 Method and logic for storing and extracting in-band multicast port information stored along with the data in a single memory without memory read cycle overhead 有权
标题翻译：用于存储和提取与单个存储器中存储的带内多播端口信息一起存储而不具有存储器读取周期开销的方法和逻辑
公开(公告)号：US06578118B1
公开(公告)日：2003-06-10
申请号：US09676171
申请日：2000-09-29
申请人： S. Babar Raza , Somnath Paul
发明人： S. Babar Raza , Somnath Paul
IPC分类号： G06F1200
CPC分类号： G06F5/10 , G06F5/065
摘要： A method for writing and reading in-band information to and from a single storage element, comprising the steps of (A) receiving the in-band information, (B) storing data in either (i) a port information register when in a first state or (ii) a memory element when in a second state and (C) storing subsequent data in the memory element. The first state and the second state may be dependent upon a block position of the in-band information.
摘要翻译：一种用于向单个存储元件写入和读取带内信息的方法，包括以下步骤：（A）接收带内信息，（B）在（i）端口信息寄存器中存储数据的步骤状态或（ii）处于第二状态的存储元件，（C）将后续数据存储在存储元件中。第一状态和第二状态可以取决于带内信息的块位置。

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