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1. 发明授权

US10394562B2 Microprocessor that fuses if-then instructions 有权
公开(公告)号：US10394562B2
公开(公告)日：2019-08-27
申请号：US15728551
申请日：2017-10-10
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/30 , G06F9/38
摘要： A microprocessor performs an If-Then (IT) instruction and an associated IT block by extracting condition information from the IT instruction and for each instruction of the IT block: determining a respective condition for the instruction using the extract condition information, translating the instruction into a microinstruction, and conditionally executing the microinstruction based on the respective condition. For a first instruction, the translating comprises fusing the IT instruction with the first IT block instruction. A hardware instruction translation unit performs the extracting, determining and translating. Execution units conditionally execute the microinstructions. The hardware instruction translation unit and execution units are distinct hardware elements and are coupled together. The hardware translation unit performs the extracting, fusing and for each instruction of the IT block the determining and translating without writing intermediate results to a system memory, without execution of other architectural instructions by the microprocessor, and/or in six clock cycles or less.

2. 发明申请

US20190095216A1 Dynamic Reconfiguration of Multi-core Processor 审中-公开
公开(公告)号：US20190095216A1
公开(公告)日：2019-03-28
申请号：US16203819
申请日：2018-11-29
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks , Darius D. Gaskins
IPC分类号： G06F9/38 , G06F9/4401 , G06F1/32 , G06F12/084 , G06F13/24 , G06F9/30 , G06F12/0808 , G06F1/04 , G06F1/12 , G06F13/42 , G06F12/0875 , G06F13/364 , G06F21/57 , H04L9/08 , G06F21/53 , H01L21/66
摘要： A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

3. 发明授权

US10126793B2 Method of managing power consumption within a multi-core microprocessor utilizing an inter-core state discovery process to identify a least power-conserving target core state of all of the cores that share the resource 有权
公开(公告)号：US10126793B2
公开(公告)日：2018-11-13
申请号：US14970354
申请日：2015-12-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Darius D. Gaskins
IPC分类号： G06F1/26 , G06F1/32 , G06F1/24 , G06F13/36 , G06F15/163 , G06F9/30 , G06F9/50 , G06F9/445 , G06F15/82 , G06F11/36 , G06F11/14
摘要： A method is provided for managing power consumption within a multi-core microprocessor. An operating system issues an operating system instruction to transition a recipient core to a targeted power and/or performance state that is one of many possible states into which a microprocessor can place a core. Each core of the microprocessor has its own target state, and different cores may have different target states. After receiving the instruction, the recipient core implements any settings associated with its target core state that wouldn't affect resources shared with other cores. The recipient core also initiates an inter-core discovery process to determine a target multi-core state of all the cores sharing the resource. The target multi-core state reflects one or more settings that match the settings of the recipient core's target core state as much as possible without lowering a performance of any resource-sharing core below that core's own target core state.

4. 发明授权

US10049217B2 Event-based apparatus and method for securing bios in a trusted computing system during execution 有权
公开(公告)号：US10049217B2
公开(公告)日：2018-08-14
申请号：US15380787
申请日：2016-12-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry
IPC分类号： G06F21/44 , G06F21/57 , H04L9/06 , G06F21/72 , G06F21/62
摘要： An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a fuse array access. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

5. 发明授权

US09910991B2 Event-based apparatus and method for securing bios in a trusted computing system during execution 有权
公开(公告)号：US09910991B2
公开(公告)日：2018-03-06
申请号：US15380661
申请日：2016-12-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry
IPC分类号： G06F21/57 , G06F9/44 , H04L29/06 , H04L9/32 , G06F13/42 , G06F9/4401
CPC分类号： G06F21/572 , G06F9/4401 , G06F13/24 , G06F13/4282 , G06F21/554 , G06F2221/2107 , H04L9/06 , H04L9/0618 , H04L9/0869 , H04L9/3231 , H04L9/3242 , H04L63/0435 , H04L63/0876 , H04L63/123
摘要： An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of an operating system call. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

6. 发明授权

US09892283B2 Decryption of encrypted instructions using keys selected on basis of instruction fetch address 有权
公开(公告)号：US09892283B2
公开(公告)日：2018-02-13
申请号：US14884502
申请日：2015-10-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： G06F21/72 , G06F9/30 , H04L9/08 , G06F21/74 , G06F12/0875 , G06F21/52 , G06F21/60 , G06F21/71 , H04L9/06
CPC分类号： G06F21/72 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/602 , G06F21/71 , G06F21/74 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： A microprocessor and method are provided for securely decrypting and executing encrypted instructions within a microprocessor. A plurality of master keys are stored in a secure memory. Encrypted instructions are fetched from an instruction cache. A set of one or more master keys are selected from the secure memory based upon an encrypted instruction fetch address. The selected set of master keys or a decryption key derived therefrom is used to decrypt the encrypted instructions fetched from the instruction cache. The decrypted instructions are then securely executed within the microprocessor. In one implementation, the master keys are intervolved with each other to produce a new decryption key with every fetch quantum. Moreover, a new set of master keys is selected with every new block of instructions.

7. 发明授权

US09836609B2 Event-based apparatus and method for securing bios in a trusted computing system during execution 有权
公开(公告)号：US09836609B2
公开(公告)日：2017-12-05
申请号：US15379974
申请日：2016-12-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry
IPC分类号： G06F21/57 , G06F9/44 , H04L29/06 , G06F13/24 , G06F13/42 , H04L9/32
CPC分类号： G06F21/572 , G06F9/4401 , G06F13/24 , G06F13/4282 , G06F21/554 , G06F2221/2107 , H04L9/06 , H04L9/0618 , H04L9/0869 , H04L9/3231 , H04L9/3242 , H04L63/0435 , H04L63/0876 , H04L63/123
摘要： An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a hard disk access. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

8. 发明授权

US09830155B2 Microprocessor using compressed and uncompressed microcode storage 有权
公开(公告)号：US09830155B2
公开(公告)日：2017-11-28
申请号：US15140010
申请日：2016-04-27
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F9/30 , G06F9/28 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30178 , G06F9/26 , G06F9/268 , G06F9/28 , G06F9/30145 , G06F9/32 , G06F9/3802
摘要： A microprocessor includes compressed and uncompressed microcode memory storages, having N-bit wide and M-bit wide addressable words, respectively, where N

9. 发明授权

US09811344B2 Core ID designation system for dynamically designated bootstrap processor 有权
公开(公告)号：US09811344B2
公开(公告)日：2017-11-07
申请号：US15357145
申请日：2016-11-21
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Stephan Gaskins
IPC分类号： G06F13/00 , G06F9/38 , G06F1/32 , G06F12/084 , G06F13/24 , G06F9/44 , G06F13/364 , G06F12/0808 , G06F9/30 , G06F12/0875 , G06F1/04 , G06F1/12 , G06F13/42 , G06F21/53 , G06F21/57 , H04L9/08 , H01L21/66
CPC分类号： G06F9/3885 , G06F1/04 , G06F1/12 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/30032 , G06F9/30047 , G06F9/30079 , G06F9/30087 , G06F9/30105 , G06F9/30145 , G06F9/3802 , G06F9/3861 , G06F9/4403 , G06F9/4405 , G06F9/4411 , G06F9/4418 , G06F12/0808 , G06F12/084 , G06F12/0875 , G06F13/24 , G06F13/364 , G06F13/42 , G06F21/53 , G06F21/57 , G06F2212/452 , G06F2212/6028 , G06F2212/62 , H01L22/34 , H04L9/0877 , H04L9/0897 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02B70/30 , Y02D10/10 , Y02D10/126 , Y02D10/128 , Y02D10/13 , Y02D10/171 , Y02D10/172 , Y02D10/30 , Y02D50/20
摘要： A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to generate a default core ID and to sample the indicator. When the indicator indicates a first predetermined value, the default core ID generated by a default one of the plurality of processing cores designates the default processing core to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to generate alternate core IDs that are different from the default core IDs. One of the alternate core IDs designates an alternate processing core, other than the default processing core, to be the bootstrap processor.

10. 发明授权

US09779242B2 Programmable secure bios mechanism in a trusted computing system 有权
公开(公告)号：US09779242B2
公开(公告)日：2017-10-03
申请号：US15338586
申请日：2016-10-31
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry
IPC分类号： G06F21/57 , H04L9/06
CPC分类号： G06F21/572 , G06F2221/2139 , H04L9/0631 , H04L9/0643
摘要： An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), a tamper detector, a random number generator, and a JTAG control chain. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest, where the encrypted message digest has an encrypted version of a first message digest that corresponds to the BIOS contents. The tamper detector is operatively coupled to the BIOS ROM, and is configured to generate a BIOS check interrupt at a combination of prescribed intervals and event occurrences, and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest, and is configured to compare the second message digest with the decrypted message digest, and is configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The random number generator disposed within the microprocessor, and generates a random number at completion of a current BIOS check, which is employed to set a following prescribed interval, whereby the prescribed intervals are randomly varied. The JTAG control chain is configured to program the combination of prescribed intervals and event occurrences within tamper detection microcode storage.

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