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1. 发明申请

US20200026684A1 CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE 审中-公开
公开(公告)号：US20200026684A1
公开(公告)日：2020-01-23
申请号：US16041473
申请日：2018-07-20
申请人： Xilinx, Inc.
发明人： Ian A. Swarbrick , Sagheer Ahmad , Ygal Arbel , Dinesh D. Gaitonde
IPC分类号： G06F15/78 , H04L12/24 , H04L12/933
摘要： An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

2. 发明授权

US10346346B1 Inline ECC function for system-on-chip 有权
公开(公告)号：US10346346B1
公开(公告)日：2019-07-09
申请号：US15851449
申请日：2017-12-21
申请人： Xilinx, Inc.
发明人： Ygal Arbel , Ian A. Swarbrick , Sagheer Ahmad
IPC分类号： G06F15/78 , G06F11/10 , G06F13/16 , G11C29/52
摘要： An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.

3. 发明申请

US20160085449A1 MANAGING MEMORY IN A MULTIPROCESSOR SYSTEM 有权
标题翻译：在多处理器系统中管理存储器
公开(公告)号：US20160085449A1
公开(公告)日：2016-03-24
申请号：US14493081
申请日：2014-09-22
申请人： Xilinx, Inc.
发明人： Ygal Arbel , Sagheer Ahmad , James J. Murray , Nishit Patel , Ahmad R. Ansari
IPC分类号： G06F3/06 , G06F9/30
CPC分类号： G06F3/0604 , G06F3/0655 , G06F3/0683 , G06F9/3004 , G06F13/1657 , G06F2003/0697
摘要： In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.
摘要翻译：在一个示例中，用于管理第一和第二微处理器之间的存储器的电路，每个微处理器耦合到控制电路，包括：第一和第二存储器电路; 以及耦合到第一和第二存储器电路以及第一和第二微处理器的存储器接口的开关电路，开关电路具有作为输入的模式信号。开关被配置为基于模式信号选择性地以第一模式或第二模式中的一个模式操作，使得在第一模式中，开关电路将第一存储器电路耦合到第一微处理器和第二存储器的存储器接口电路连接到第二微处理器的存储器接口，并且在第二模式中，开关电路选择性地将第一或第二存储器电路耦合到第一或第二微处理器的存储器接口。

4. 发明申请

US20150356027A1 CIRCUITS FOR AND METHODS OF ENABLING THE ACCESS TO DATA 有权
标题翻译：电路访问数据的方法和方法
公开(公告)号：US20150356027A1
公开(公告)日：2015-12-10
申请号：US14301008
申请日：2014-06-10
申请人： Xilinx, Inc.
发明人： Ygal Arbel , James J. Murray , Hyun W. Kwon , Nishit Patel
IPC分类号： G06F12/14 , G06F13/30
CPC分类号： G06F12/145 , G06F13/00 , G06F13/28 , G06F13/30
摘要： A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.
摘要翻译：描述了一种能够访问数据的电路。该电路包括存储具有第一预定大小的数据块的存储器件; 以及直接存储器访问电路，其耦合到所述存储器件，所述直接存储器电路访问具有大于所述第一预定大小的第二预定尺寸的数据有效载荷; 其中所述直接存储器访问电路响应于具有对应于存储在所述存储器件中的预定数量的数据块的多个地址的描述符来访问所述数据有效载荷。还公开了一种能够访问数据的方法。

5. 发明授权

US09047474B1 Circuits for and methods of providing isolation in an integrated circuit 有权
标题翻译：在集成电路中提供隔离的电路和方法
公开(公告)号：US09047474B1
公开(公告)日：2015-06-02
申请号：US14187143
申请日：2014-02-21
申请人： Xilinx, Inc.
发明人： Sagheer Ahmad , Bradley L. Taylor , Ygal Arbel
IPC分类号： H03K19/00 , G06F21/60 , H03K19/177
CPC分类号： H03K19/17768 , G06F21/575 , G06F21/74
摘要： A circuit for providing isolation in an integrated circuit is described. The circuit comprises a first circuit block having circuits associated with a first security level; a second circuit block having circuits associated with a second security level; and a third circuit block having programmable resources, the third circuit block providing isolation between the first circuit block and the second circuit block and being programmable to enable connections between the first circuit block and the second circuit block.
摘要翻译：描述了用于在集成电路中提供隔离的电路。该电路包括具有与第一安全级相关联的电路的第一电路块; 具有与第二安全级相关联的电路的第二电路块; 以及具有可编程资源的第三电路块，所述第三电路块提供所述第一电路块和所述第二电路块之间的隔离并且可编程以使得所述第一电路块和所述第二电路块之间能够连接。

6. 发明授权

US10673745B2 End-to-end quality-of-service in a network-on-chip 审中-公开
公开(公告)号：US10673745B2
公开(公告)日：2020-06-02
申请号：US15886583
申请日：2018-02-01
申请人： Xilinx, Inc.
发明人： Ian A. Swarbrick , Ygal Arbel , Millind Mittal , Sagheer Ahmad
IPC分类号： H04L12/725 , H04L12/851 , G06F15/78 , H04L12/931 , H04L29/08 , H04W4/50 , H04L12/933 , H04L12/701 , H04L12/70 , H04L12/863 , H04L12/721
摘要： An example method of generating a configuration for a network on chip (NoC) in a programmable device includes: receiving traffic flow requirements for a plurality of traffic flows; assigning routes through the NoC for each traffic flow based on the traffic flow requirements; determining arbitration settings for the traffic flows along the assigned routes; generating programming data for the NoC; and loading the programming data to the programmable device to configure the NoC.

7. 发明申请

US20190238453A1 END-TO-END QUALITY-OF-SERVICE IN A NETWORK-ON-CHIP 审中-公开
公开(公告)号：US20190238453A1
公开(公告)日：2019-08-01
申请号：US15886583
申请日：2018-02-01
申请人： Xilinx, Inc.
发明人： Ian A. Swarbrick , Ygal Arbel , Millind Mittal , Sagheer Ahmad
IPC分类号： H04L12/725 , H04L12/851 , H04L12/931 , G06F15/78
摘要： An example method of generating a configuration for a network on chip (NoC) in a programmable device includes: receiving traffic flow requirements for a plurality of traffic flows; assigning routes through the NoC for each traffic flow based on the traffic flow requirements; determining arbitration settings for the traffic flows along the assigned routes; generating programming data for the NoC; and loading the programming data to the programmable device to configure the NoC.

8. 发明申请

US20190196901A1 INLINE ECC FUNCTION FOR SYSTEM-ON-CHIP 审中-公开
公开(公告)号：US20190196901A1
公开(公告)日：2019-06-27
申请号：US15851449
申请日：2017-12-21
申请人： Xilinx, Inc.
发明人： Ygal Arbel , Ian A. Swarbrick , Sagheer Ahmad
IPC分类号： G06F11/10 , G11C29/52 , G06F13/16 , G06F15/78
CPC分类号： G06F15/7825 , G06F11/10 , G06F11/1068 , G06F13/1668 , G11C29/52
摘要： An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.

9. 发明申请

US20190050252A1 ADAPTIVE QUALITY OF SERVICE CONTROL CIRCUIT 审中-公开
公开(公告)号：US20190050252A1
公开(公告)日：2019-02-14
申请号：US15673220
申请日：2017-08-09
申请人： Xilinx, Inc.
发明人： Ygal Arbel
IPC分类号： G06F9/46 , G06F13/16 , G06F15/78 , G06F3/06
CPC分类号： G06F9/467 , G06F3/061 , G06F3/0628 , G06F3/064 , G06F11/3027 , G06F11/349 , G06F13/1621 , G06F13/1668 , G06F15/7807
摘要： Disclosed approaches of controlling quality of service in servicing memory transactions includes periodically reading by a quality of service management (QM) circuit, respective first data rate metrics and respective latency metrics from requester circuits while the requester circuits are actively transmitting memory transactions to a memory controller. The QM circuit periodically reads a second data rate metric from the memory controller while the memory controller is processing the memory transactions, and determines, while the requester circuits are actively transmitting memory transactions to the memory controller, whether or not the respective first data rate metrics, respective latency metrics, and second data rate metric satisfy a quality of service metric. In response to determining that the operating metrics do not satisfy the quality of service metric, the QM circuit dynamically changes value(s) of a control parameter(s) of the requester circuit(s) and of the memory controller.

10. 发明授权

US09213866B1 Circuits for and methods of preventing unauthorized access in an integrated circuit 有权
标题翻译：集成电路中防止未经授权访问的电路和方法
公开(公告)号：US09213866B1
公开(公告)日：2015-12-15
申请号：US14242268
申请日：2014-04-01
申请人： Xilinx, Inc.
发明人： Sagheer Ahmad , Ygal Arbel
IPC分类号： G06F21/76 , G06F21/78
CPC分类号： G06F21/76
摘要： A circuit for preventing unauthorized access in an integrated circuit includes a plurality of circuit block and a plurality of protection circuits. Each protection circuit is coupled to an input of a corresponding circuit block of the plurality of circuit blocks. Each protection circuit determines whether an access request to the corresponding circuit block is authorized. The protection circuits could be implemented to monitor system-on-chip interconnections of master and slave circuits, for example. A method of preventing unauthorized access in an integrated circuit could be implemented using the circuit.
摘要翻译：用于防止集成电路中的未授权访问的电路包括多个电路块和多个保护电路。每个保护电路耦合到多个电路块的相应电路块的输入端。每个保护电路确定对相应电路块的访问请求是否被授权。例如，可以实施保护电路来监视主电路和从电路的片上系统互连。可以使用该电路来实现防止集成电路中的未授权访问的方法。

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