会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明申请
    • ELECTRONIC DEVICE
    • 电子设备
    • US20140355190A1
    • 2014-12-04
    • US14079650
    • 2013-11-14
    • Hsin YehYung-Hsiang ChenWei-Han HuTzu-Chien LaiCho-Yao Yen
    • Hsin YehYung-Hsiang ChenWei-Han HuTzu-Chien LaiCho-Yao Yen
    • G06F1/16
    • G06F1/1669
    • An electronic device including a first body and a second body is provided. The first body has a first connection end. The second body has a second connection end, in which the second connection end has a first magnetic component and a first convex arc surface, and the second body is detachably connected to the first body through a magnetic attractive force between the first magnetic component and the first connection end. The first body and the second body are configured to rotate around a rotation axis relatively to each other, and the first convex arc surface faces the first connection end and extends along a direction parallel to the rotation axis.
    • 提供了包括第一主体和第二主体的电子装置。 第一个主体有第一个连接端。 第二主体具有第二连接端,其中第二连接端具有第一磁性部件和第一凸起弧形表面,并且第二主体通过第一磁性部件和第一磁性部件之间的磁性吸引力可拆卸地连接到第一主体 第一连接端。 第一主体和第二主体被构造为围绕彼此相对旋转的轴线旋转,并且第一凸弧面面向第一连接端并沿着平行于旋转轴线的方向延伸。
    • 7. 发明申请
    • STRUCTURE AND METHOD FOR E-BEAM IN-CHIP OVERLAY MARK
    • 电子束芯片覆盖标记的结构和方法
    • US20130147066A1
    • 2013-06-13
    • US13314644
    • 2011-12-08
    • Dong-Hsu ChengMing-Ho TsaiChih-Chung HuangYung-Hsiang ChenChun-Hung Chen
    • Dong-Hsu ChengMing-Ho TsaiChih-Chung HuangYung-Hsiang ChenChun-Hung Chen
    • H01L23/544H01L21/762
    • H01L22/12G03F7/70633
    • The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.
    • 本公开提供了一种集成电路结构,其包括具有第一区域的半导体衬底和具有小于约10微米×10微米的面积的第二区域; 半导体衬底上的第一材料层,并被图案化以具有第一区域中的第一电路特征和第二区域中的第一标记; 以及在所述第一材料层之上的第二材料层,并被图案化以具有所述第一区域中的第二电路特征和所述第二区域中的第二标记。 第一标记包括沿第一方向定向的第一标记特征,以及在垂直于第一方向的第二方向上定向的第二标记特征。 第二标记包括沿第一方向定向的第三标记特征,第四标记特征指向第二方向。