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1. 发明申请

US20100032771A1 SHORT-CHANNEL SCHOTTKY-BARRIER MOSFET DEVICE AND MANUFACTURING METHOD 审中-公开
标题翻译：短路肖特基栅极MOSFET器件及制造方法
公开(公告)号：US20100032771A1
公开(公告)日：2010-02-11
申请号：US12581097
申请日：2009-10-16
申请人： John P. Snyder
发明人： John P. Snyder
IPC分类号： H01L29/78
CPC分类号： H01L21/823835 , H01L21/823412 , H01L21/823418 , H01L21/82345 , H01L27/095 , H01L29/665 , H01L29/66643 , H01L29/7839 , H01L2924/0002 , H01L2924/00
摘要： A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the present invention unconditionally eliminates the parasitic bipolar gain associated with MOSFET fabrication, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art.
摘要翻译：公开了一种MOSFET器件及其制造方法。本发明在MOSFET器件结构的上下文中利用用于源极和/或漏极接触制造的肖特基势垒接触，以消除对光晕/凹穴注入和浅源极/漏极扩展的需求以控制短沟道效应。此外，本发明无条件地消除与MOSFET制造相关的寄生双极增益，降低了制造成本，加强了器件性能参数的控制，并且与现有技术相比提供了优异的器件特性。

2. 发明授权

US08058167B2 Dynamic Schottky barrier MOSFET device and method of manufacture 有权
标题翻译：动态肖特基势垒MOSFET器件及其制造方法
公开(公告)号：US08058167B2
公开(公告)日：2011-11-15
申请号：US12568655
申请日：2009-09-28
申请人： John P. Snyder , John M. Larson
发明人： John P. Snyder , John M. Larson
IPC分类号： H01L21/44
CPC分类号： H01L29/66643 , H01L29/0653 , H01L29/0895 , H01L29/6656 , H01L29/66636 , H01L29/7839
摘要： A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.
摘要翻译：提供一种用于调节电流流动的装置及其制造方法。该器件包括形成肖特基势垒或肖特基状结到半导体衬底的金属 - 绝缘体 - 半导体源极 - 漏极接触。该器件包括在半导体衬底和金属源极和/或漏极之间的界面层，从而通过施加不同的偏置条件来动态地调节肖特基势垒高度。动态肖特基势垒调制为低漏极偏置条件提供了增加的电流，降低了肖特基势垒MOSFET器件的亚线性导通特性并提高器件性能。

3. 发明授权

US08022459B2 Metal source and drain transistor having high dielectric constant gate insulator 有权
标题翻译：具有高介电常数栅极绝缘体的金属源极和漏极晶体管
公开(公告)号：US08022459B2
公开(公告)日：2011-09-20
申请号：US12719760
申请日：2010-03-08
申请人： John P. Snyder , John M. Larson
发明人： John P. Snyder , John M. Larson
IPC分类号： H01L27/108
CPC分类号： H01L21/28194 , H01L21/26513 , H01L21/28167 , H01L21/28176 , H01L21/28185 , H01L21/823412 , H01L27/095 , H01L29/105 , H01L29/1054 , H01L29/47 , H01L29/51 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66643 , H01L29/7839
摘要： The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.
摘要翻译：本发明涉及一种用于通过高介电常数栅极绝缘层和形成具有衬底的肖特基接触或肖特基状区域的源极和/或漏极来调节电流的装置及其制造方法。在一个方面，栅极绝缘层的介电常数大于硅的介电常数。在另一方面，电流调节装置可以是具有任何取向的MOSFET器件，可选地是平面P型或N型MOSFET。在另一方面，源极和/或漏极可部分或全部由硅化物组成。

4. 发明授权

US07939902B2 Field effect transistor having source and/or drain forming schottky or schottky-like contact with strained semiconductor substrate 失效
标题翻译：具有与应变半导体衬底的源极和/或漏极形成肖特基或肖特基状接触的场效应晶体管
公开(公告)号：US07939902B2
公开(公告)日：2011-05-10
申请号：US12567659
申请日：2009-09-25
申请人： John P. Snyder , John M. Larson
发明人： John P. Snyder , John M. Larson
IPC分类号： H01L31/102
CPC分类号： H01L29/0847 , H01L21/28194 , H01L21/823412 , H01L29/105 , H01L29/1054 , H01L29/47 , H01L29/51 , H01L29/517 , H01L29/665 , H01L29/66643 , H01L29/7839
摘要： The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.
摘要翻译：本发明是具有应变半导体衬底和肖特基势垒源极和漏极的场效应晶体管及其制造方法。与传统器件相比，肖特基势垒场效应晶体管的体电荷载流子传输特性使载流子表面散射最小化，这使得应变衬底能够在该器件中提供改进的功率和速度性能特性。

5. 发明授权

US07821075B2 CMOS device with zero soft error rate 有权
标题翻译：具有零软错误率的CMOS器件
公开(公告)号：US07821075B2
公开(公告)日：2010-10-26
申请号：US11546829
申请日：2006-10-12
申请人： John P. Snyder , John M. Larson
发明人： John P. Snyder , John M. Larson
IPC分类号： H01L27/095 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/823892 , H01L21/823814 , H01L27/0921 , H01L29/66636 , H01L29/66643 , H01L29/7839
摘要： A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.
摘要翻译：提供了一种CMOS器件和制造方法，用于产生不易受各种软错误（例如单事件颠簸，多位异常或单事件闭锁）的集成电路的影响。 CMOS器件和方法利用新的和新颖的结构与金属源极/漏电极的结构，以消除软错误。在一个实施例中，CMOS器件使用用于NMOS器件的第一金属源/漏极材料和用于PMOS器件的第二金属源极/漏极材料。 CMOS器件还使用具有用于PMOS器件的浅N阱和掩埋P阱的多层阱结构以及用于NMOS器件的浅P阱和掩埋N阱。

6. 发明申请

US20100213556A1 METAL SOURCE AND DRAIN TRANSISTOR HAVING HIGH DIELECTRIC CONSTANT GATE INSULATOR 有权
标题翻译：具有高介电常数门绝缘体的金属源和漏极晶体管
公开(公告)号：US20100213556A1
公开(公告)日：2010-08-26
申请号：US12719760
申请日：2010-03-08
申请人： John P. Snyder , John M. Larson
发明人： John P. Snyder , John M. Larson
IPC分类号： H01L29/78 , H01L29/417
CPC分类号： H01L21/28194 , H01L21/26513 , H01L21/28167 , H01L21/28176 , H01L21/28185 , H01L21/823412 , H01L27/095 , H01L29/105 , H01L29/1054 , H01L29/47 , H01L29/51 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66643 , H01L29/7839
摘要： The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.
摘要翻译：本发明涉及一种用于通过高介电常数栅极绝缘层和形成具有衬底的肖特基接触或肖特基状区域的源极和/或漏极来调节电流的装置及其制造方法。在一个方面，栅极绝缘层的介电常数大于硅的介电常数。在另一方面，电流调节装置可以是具有任何取向的MOSFET器件，可选地是平面P型或N型MOSFET。在另一方面，源极和/或漏极可部分或全部由硅化物组成。

7. 发明申请

US20100015802A1 DYNAMIC SCHOTTKY BARRIER MOSFET DEVICE AND METHOD OF MANUFACTURE 有权
标题翻译：动态肖特基栅极MOSFET器件及其制造方法
公开(公告)号：US20100015802A1
公开(公告)日：2010-01-21
申请号：US12568655
申请日：2009-09-28
申请人： John P. Snyder , John M. Larson
发明人： John P. Snyder , John M. Larson
IPC分类号： H01L21/283
CPC分类号： H01L29/66643 , H01L29/0653 , H01L29/0895 , H01L29/6656 , H01L29/66636 , H01L29/7839
摘要： A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.
摘要翻译：提供一种用于调节电流流动的装置及其制造方法。该器件包括形成肖特基势垒或肖特基状结到半导体衬底的金属 - 绝缘体 - 半导体源极 - 漏极接触。该器件包括在半导体衬底和金属源极和/或漏极之间的界面层，从而通过施加不同的偏置条件来动态地调节肖特基势垒高度。动态肖特基势垒调制为低漏极偏置条件提供了增加的电流，降低了肖特基势垒MOSFET器件的亚线性导通特性并提高器件性能。

8. 发明申请

US20100013015A1 METAL SOURCE/DRAIN SCHOTTKY BARRIER SILICON-ON-NOTHING MOSFET DEVICE 审中-公开
标题翻译：金属源/漏极肖特基栅极无硅绝缘MOSFET器件
公开(公告)号：US20100013015A1
公开(公告)日：2010-01-21
申请号：US12569895
申请日：2009-09-29
申请人： John P. Snyder
发明人： John P. Snyder
IPC分类号： H01L29/786
CPC分类号： H01L29/66636 , H01L29/41733 , H01L29/458 , H01L29/66643 , H01L29/66651 , H01L29/66772 , H01L29/7839 , H01L29/78618 , H01L29/78654
摘要： A Schottky barrier MOSFET (SB-MOS) device and a method of manufacturing having a silicon-on-nothing (SON) architecture in a channel region are provided. More specifically, metal source/drain SB-MOS devices are provided in combination with a channel structure comprising a semiconductor channel region such as silicon isolated from a bulk substrate by an SON dielectric layer. In one embodiment, the SON dielectric layer has a triple stack structure comprising oxide on nitride on oxide, which is in contact with the underlying semiconductor substrate.
摘要翻译：提供肖特基势垒MOSFET（SB-MOS）器件和在通道区域中具有无硅无底层（SON）架构的制造方法。更具体地，金属源极/漏极SB-MOS器件与包括半导体沟道区（例如通过SON介电层从体衬底隔离的硅）的沟道结构组合提供。在一个实施例中，SON介电层具有三重堆叠结构，其包含与氧化物上的氧化物，其与下面的半导体衬底接触。

9. 发明申请

US20100006949A1 SCHOTTKY BARRIER CMOS DEVICE AND METHOD 有权
标题翻译：肖特基屏障CMOS器件及方法
公开(公告)号：US20100006949A1
公开(公告)日：2010-01-14
申请号：US12562131
申请日：2009-09-18
申请人： John P. Snyder , John M. Larson
发明人： John P. Snyder , John M. Larson
IPC分类号： H01L27/092
CPC分类号： H01L29/7839 , H01L27/095 , H01L29/517
摘要： A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.
摘要翻译：公开了CMOS器件和制造方法。本发明在CMOS器件和CMOS集成电路的上下文中利用肖特基势垒触点来制造源极和/或漏极接触，以消除对光晕/凹穴注入的需求，用于控制短沟道效应的浅源极/漏极扩展，良好注入步骤和复杂的设备隔离步骤。此外，本发明消除了与CMOS器件操作相关联的寄生双极增益，降低了制造成本，加强了器件性能参数的控制，并且与现有技术相比提供了优异的器件特性。在一个实施例中，本发明使用硅化物排除掩模工艺来形成用于形成CMOS器件的互补PMOS和NMOS器件的双硅化物肖特基势垒源和/或漏极接触。

10. 发明申请

US20120126311A1 POWER TRANSISTOR WITH METAL SOURCE AND METHOD OF MANUFACTURE 审中-公开
标题翻译：具有金属源的功率晶体管及其制造方法
公开(公告)号：US20120126311A1
公开(公告)日：2012-05-24
申请号：US13271218
申请日：2011-10-11
申请人： John P. Snyder
发明人： John P. Snyder
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0839 , H01L29/1083 , H01L29/41741 , H01L29/66643 , H01L29/7397 , H01L29/7813 , H01L29/7839 , H01L29/872
摘要： A metal source power transistor device and method of manufacture is provided, wherein the metal source power transistor having a source which is comprised of metal and which forms a Schottky barrier with the body region and channel region of the transistor. The metal source power transistor is unconditionally immune from parasitic bipolar action and, therefore, the effects of snap-back and latch-up, without the need for a body contact. The ability to allow the body to float in the metal source power transistor reduces the process complexity and allows for more compact device layout.
摘要翻译：提供了一种金属源功率晶体管器件及其制造方法，其中金属源功率晶体管具有由金属构成的源极，并与晶体管的体区和沟道区形成肖特基势垒。金属源功率晶体管无条件地免受寄生双极性作用，因此无需身体接触，即可实现卡扣和闩锁的效果。允许身体漂浮在金属源功率晶体管中的能力降低了工艺复杂性，并允许更紧凑的器件布局。

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