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1. 发明申请

US20100238728A1 Method and apparatus of operating a non-volatile DRAM 有权
标题翻译：操作非易失性DRAM的方法和装置
公开(公告)号：US20100238728A1
公开(公告)日：2010-09-23
申请号：US12800894
申请日：2010-05-25
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C14/00 , G11C16/06
CPC分类号： G11C11/404 , G11C11/4072 , G11C11/4076 , G11C14/0018 , G11C16/0416 , G11C16/10
摘要： A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by positively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully charged. The pass-gate transistor is activated and if the pass-gate transistor is erased it does not turn on and if it is programmed, it turns on. Charge is shared on the complementary pair of pre-charged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in to the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished Gate-induced drain-lowering (GIDL) assisted band-to-band tunneling and Fowler-Nordheim tunneling respectively. Programming or erasing a selected row of cells does not affect the data states of the cells in the unselected rows.
摘要翻译：非易失性DRAM单元包括通过栅极晶体管和单元电容器。非易失性单元的读取操作通过对单元电容器正向充电而开始。相关联的虚拟非易失性DRAM单元的单元电容器被完全充电。激活栅极晶体管，如果栅极晶体管被擦除，它将不会导通，如果被编程，它将导通。电荷在连接到非易失性DRAM单元及其相关联的虚拟非易失性DRAM单元的互补预充电位线对上共享。读出放大器检测存储在通过栅极晶体管中的数据状态的差异。非易失性DRAM单元的编程和擦除分别实现了栅极引起的漏极降低（GIDL）辅助带对带隧道和Fowler-Nordheim隧道。编辑或删除选定的单元格行不会影响未选择行中的单元格的数据状态。

2. 发明授权

US08228726B2 N-channel SONOS non-volatile memory for embedded in logic 有权
标题翻译：用于嵌入逻辑的N沟道SONOS非易失性存储器
公开(公告)号：US08228726B2
公开(公告)日：2012-07-24
申请号：US12906153
申请日：2010-10-18
申请人： Gang-Feng Fang , Wingyu Leung
发明人： Gang-Feng Fang , Wingyu Leung
IPC分类号： G11C16/04 , H01L29/788 , H01L21/336
CPC分类号： H01L27/11565 , G11C16/0466 , G11C16/28 , H01L27/11568 , H01L27/11573
摘要： A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least one non-volatile memory cell consists of a SONOS transistor fabricated on a P substrate, with a deep N-well located in the P substrate, with a P-well located in the deep N-well. The memory cell further includes an access NMOS transistor, coupled to the SONOS transistor and located in the same P-well that includes an oxide only gate-dielectric. The cell can be fabricated in a modified logic process with other transistors and with their physical characteristics preserved.
摘要翻译：公开了一种通过添加ONO沉积和蚀刻的单一多逻辑工艺制造的电可编程和可擦除非易失性存储单元的系统和方法。在一个实施例中，非易失性存储器系统包括至少一个非易失性存储器单元，其由在P衬底上制造的SONOS晶体管构成，其中深N阱位于P衬底中，P阱位于深N井存储单元还包括一个访问NMOS晶体管，其耦合到SONOS晶体管并且位于包括仅氧化物栅电介质的相同P阱中。电池可以用其他晶体管的修改逻辑工艺制造，并保留其物理特性。

3. 发明申请

US20120026794A1 Method and apparatus of operating a non-volatile DRAM 有权
标题翻译：操作非易失性DRAM的方法和装置
公开(公告)号：US20120026794A1
公开(公告)日：2012-02-02
申请号：US13317115
申请日：2011-10-11
申请人： Wingyu Lueng
发明人： Wingyu Lueng
IPC分类号： G11C14/00
CPC分类号： G11C16/0416 , G11C11/404 , G11C11/4072 , G11C11/4076 , G11C14/0018 , G11C16/10
摘要： A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is programmed it does not turn on and if it is erased, it turns on. Charge is shared on the complementary pair of precharged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate to transistor. The program and erase of the non-volatile DRAM cell is accomplished by charge injection from the associated bit line of the non-volatile DRAM cell.
摘要翻译：非易失性DRAM单元包括通过栅极晶体管和单元电容器。非易失性单元的读取操作开始于对单元电容器进行负充电。相关联的虚拟非易失性DRAM单元的单元电容器被完全放电。激活栅极晶体管，如果通过栅极晶体管被编程，它将不会导通，如果被擦除，它将导通。电荷在连接到非易失性DRAM单元及其相关联的虚拟非易失性DRAM单元的互补预充电位线对上共享。读出放大器检测存储在栅极中的数据状态与晶体管的差异。非易失性DRAM单元的编程和擦除通过从非易失性DRAM单元的相关位线的电荷注入来实现。

4. 发明申请

US20110032766A1 N-CHANNEL SONOS NON-VOLATILE MEMORY FOR EMBEDDED IN LOGIC 有权
标题翻译： N-CHANNEL SONOS用于嵌入逻辑的非易失性存储器
公开(公告)号：US20110032766A1
公开(公告)日：2011-02-10
申请号：US12906153
申请日：2010-10-18
申请人： GANG-FENG FANG , Wingyu Leung
发明人： GANG-FENG FANG , Wingyu Leung
IPC分类号： G11C16/04 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11565 , G11C16/0466 , G11C16/28 , H01L27/11568 , H01L27/11573
摘要： A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least one non-volatile memory cell consists of a SONOS transistor fabricated on a P substrate, with a deep N-well located in the P substrate, with a P-well located in the deep N-well. The memory cell further includes an access NMOS transistor, coupled to the SONOS transistor and located in the same P-well that includes an oxide only gate-dielectric. The cell can be fabricated in a modified logic process with other transistors and with their physical characteristics preserved.
摘要翻译：公开了一种通过添加ONO沉积和蚀刻的单一多逻辑工艺制造的电可编程和可擦除非易失性存储单元的系统和方法。在一个实施例中，非易失性存储器系统包括至少一个非易失性存储器单元，其由制造在P衬底上的SONOS晶体管和位于P衬底中的深N阱组成，P阱位于深N井存储单元还包括一个访问NMOS晶体管，其耦合到SONOS晶体管并且位于包括仅氧化物栅电介质的相同P阱中。电池可以用其他晶体管的修改逻辑工艺制造，并保留其物理特性。

5. 发明授权

US08489843B2 Configurable memory device 有权
标题翻译：可配置的存储设备
公开(公告)号：US08489843B2
公开(公告)日：2013-07-16
申请号：US12763240
申请日：2010-04-20
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0292 , G06F2212/205 , G06F2212/7201
摘要： A method includes forming a memory device through providing an array of non-volatile memory cells including one or more non-volatile memory cell(s) and an array of volatile memory cells including one or more volatile memory cell(s) on a substrate. The method also includes appropriately programming an address translation logic associated with the memory device through a set of registers associated therewith to enable configurable mapping of an address associated with a sector of the memory device to any memory address space location in a computing system associated with the memory device. The address translation logic is configured to enable translation of an external virtual address associated with the sector of the memory device to a physical address associated therewith.
摘要翻译：一种方法包括通过提供包括一个或多个非易失性存储器单元的非易失性存储器单元阵列和在衬底上包括一个或多个易失性存储器单元的易失性存储器单元的阵列来形成存储器件。该方法还包括通过与其相关联的一组寄存器适当地编程与存储器设备相关联的地址转换逻辑，以使与存储器设备的扇区相关联的地址的可配置映射与与该存储器设备相关联的计算系统中的任何存储器地址空间位置存储设备。地址转换逻辑被配置为使得能够将与存储器设备的扇区相关联的外部虚拟地址转换为与其相关联的物理地址。

6. 发明授权

US08391078B2 Method and apparatus of operating a non-volatile DRAM 有权
标题翻译：操作非易失性DRAM的方法和装置
公开(公告)号：US08391078B2
公开(公告)日：2013-03-05
申请号：US12800894
申请日：2010-05-25
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/404 , G11C11/4072 , G11C11/4076 , G11C14/0018 , G11C16/0416 , G11C16/10
摘要： A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by positively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully charged. The pass-gate transistor is activated and if the pass-gate transistor is erased it does not turn on and if it is programmed, it turns on. Charge is shared on the complementary pair of pre-charged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished Gate-induced drain-lowering (GIDL) assisted band-to-band tunneling and Fowler-Nordheim tunneling respectively. Programming or erasing a selected row of cells does not affect the data states of the cells in the unselected rows.
摘要翻译：非易失性DRAM单元包括通过栅极晶体管和单元电容器。非易失性单元的读取操作通过对单元电容器正向充电而开始。相关联的虚拟非易失性DRAM单元的单元电容器被完全充电。激活栅极晶体管，如果栅极晶体管被擦除，它将不会导通，如果被编程，它将导通。电荷在连接到非易失性DRAM单元及其相关联的虚拟非易失性DRAM单元的互补预充电位线对上共享。读出放大器检测存储在通过栅极晶体管中的数据状态的差异。非易失性DRAM单元的编程和擦除分别实现了栅极引起的漏极降低（GIDL）辅助带对带隧道和Fowler-Nordheim隧道。编辑或删除选定的单元格行不会影响未选择行中的单元格的数据状态。

7. 发明授权

US08320190B2 Method and apparatus of operating a non-volatile DRAM 有权
标题翻译：操作非易失性DRAM的方法和装置
公开(公告)号：US08320190B2
公开(公告)日：2012-11-27
申请号：US13317115
申请日：2011-10-11
申请人： Wingyu Lueng
发明人： Wingyu Lueng
IPC分类号： G11C11/34
CPC分类号： G11C16/0416 , G11C11/404 , G11C11/4072 , G11C11/4076 , G11C14/0018 , G11C16/10
摘要： A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is programmed it does not turn on and if it is erased, it turns on. Charge is shared on the complementary pair of precharged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished by charge injection from the associated bit line of the non-volatile DRAM cell.
摘要翻译：非易失性DRAM单元包括通过栅极晶体管和单元电容器。非易失性单元的读取操作开始于对单元电容器进行负充电。相关联的虚拟非易失性DRAM单元的单元电容器被完全放电。激活栅极晶体管，如果通过栅极晶体管被编程，它将不会导通，如果被擦除，它将导通。电荷在连接到非易失性DRAM单元及其相关联的虚拟非易失性DRAM单元的互补的预充电位线对上共享。读出放大器检测存储在通过栅极晶体管中的数据状态的差异。非易失性DRAM单元的编程和擦除通过从非易失性DRAM单元的相关位线的电荷注入来实现。

8. 发明申请

US20110258364A1 CONFIGURABLE MEMORY DEVICE 有权
标题翻译：可配置存储器件
公开(公告)号：US20110258364A1
公开(公告)日：2011-10-20
申请号：US12763240
申请日：2010-04-20
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G06F12/00 , G06F12/10 , G06F12/02
CPC分类号： G06F12/0246 , G06F12/0292 , G06F2212/205 , G06F2212/7201
摘要： A method includes forming a memory device through providing an array of non-volatile memory cells including one or more non-volatile memory cell(s) and an array of volatile memory cells including one or more volatile memory cell(s) on a substrate. The method also includes appropriately programming an address translation logic associated with the memory device through a set of registers associated therewith to enable configurable mapping of an address associated with a sector of the memory device to any memory address space location in a computing system associated with the memory device. The address translation logic is configured to enable translation of an external virtual address associated with the sector of the memory device to a physical address associated therewith.
摘要翻译：一种方法包括通过提供包括一个或多个非易失性存储器单元的非易失性存储器单元阵列和在衬底上包括一个或多个易失性存储器单元的易失性存储器单元的阵列来形成存储器件。该方法还包括通过与其相关联的一组寄存器适当地编程与存储器设备相关联的地址转换逻辑，以使与存储器设备的扇区相关联的地址的可配置映射与与该存储器设备相关联的计算系统中的任何存储器地址空间位置存储设备。地址转换逻辑被配置为使得能够将与存储器设备的扇区相关联的外部虚拟地址转换为与其相关联的物理地址。

9. 发明授权

US08059471B2 Method and apparatus of operating a non-volatile DRAM 有权
标题翻译：操作非易失性DRAM的方法和装置
公开(公告)号：US08059471B2
公开(公告)日：2011-11-15
申请号：US12316436
申请日：2008-12-12
申请人： Wingyu Lueng
发明人： Wingyu Lueng
IPC分类号： G11C11/34
CPC分类号： G11C16/0416 , G11C11/404 , G11C11/4072 , G11C11/4076 , G11C14/0018 , G11C16/10
摘要： A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is programmed it does not turn on and if it is erased, it turns on. Charge is shared on the complementary pair of precharged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished by charge injection from the associated bit line of the non-volatile DRAM cell.
摘要翻译：非易失性DRAM单元包括通过栅极晶体管和单元电容器。非易失性单元的读取操作开始于对单元电容器进行负充电。相关联的虚拟非易失性DRAM单元的单元电容器被完全放电。激活栅极晶体管，如果通过栅极晶体管被编程，它将不会导通，如果被擦除，它将导通。电荷在连接到非易失性DRAM单元及其相关联的虚拟非易失性DRAM单元的互补的预充电位线对上共享。读出放大器检测存储在通过栅极晶体管中的数据状态的差异。非易失性DRAM单元的编程和擦除通过从非易失性DRAM单元的相关位线的电荷注入来实现。

10. 发明申请

US20090201730A1 Method and apparatus of operating a non-volatile DRAM 有权
标题翻译：操作非易失性DRAM的方法和装置
公开(公告)号：US20090201730A1
公开(公告)日：2009-08-13
申请号：US12316436
申请日：2008-12-12
申请人： Wingyu Lueng
发明人： Wingyu Lueng
IPC分类号： G11C16/04 , G11C16/06 , G11C11/24 , G11C7/00
CPC分类号： G11C16/0416 , G11C11/404 , G11C11/4072 , G11C11/4076 , G11C14/0018 , G11C16/10
摘要： A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is programmed it does not turn on and if it is erased, it turns on. Charge is shared on the complementary pair of precharged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished by charge injection from the associated bit line of the non-volatile DRAM cell.
摘要翻译：非易失性DRAM单元包括通过栅极晶体管和单元电容器。非易失性单元的读取操作开始于对单元电容器进行负充电。相关联的虚拟非易失性DRAM单元的单元电容器被完全放电。激活栅极晶体管，如果通过栅极晶体管被编程，它将不会导通，如果被擦除，它将导通。在连接到非易失性DRAM单元及其相关联的虚拟非易失性DRAM单元的互补的一对预充电位线上共享电荷。读出放大器检测存储在通过栅极晶体管中的数据状态的差异。非易失性DRAM单元的编程和擦除通过从非易失性DRAM单元的相关位线的电荷注入来实现。

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