专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11567767B2 Method and apparatus for front end gather/scatter memory coalescing 有权
公开(公告)号：US11567767B2
公开(公告)日：2023-01-31
申请号：US16944141
申请日：2020-07-30
申请人： Marvell Asia Pte, Ltd. , Cray Inc.
发明人： Harold Wade Cain, III , Rabin Andrew Sugumar , Nagesh Bangalore Lakshminarayana , Daniel Jonathan Ernst , Sanyam Mehta
IPC分类号： G06F9/30 , G06F9/38
摘要： A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.

2. 发明授权

US10903543B2 PCB transmission lines having reduced loss 有权
公开(公告)号：US10903543B2
公开(公告)日：2021-01-26
申请号：US15370498
申请日：2016-12-06
申请人： Cray Inc.
发明人： Andy Becker
IPC分类号： H01P3/08 , H01P3/02 , H05K1/02 , H01P11/00
摘要： Signal transmission structures within a printed circuit are formed to have reduced loss by making specific accommodations to reduce the surface roughness of an adjacent power plane, and thereby reducing the effects of magnetically induced currents. The power plane structure will retain sufficient surface roughness to accommodate manufacturing operations, while also contributing to reduced signal transmission losses in the adjacent signal transmission structure. The transmission structures thereby being capable of more efficiently transmitting high speed signals without undesired attenuation and loss.

3. 发明授权

US10185659B2 Memory allocation system for multi-tier memory 有权
公开(公告)号：US10185659B2
公开(公告)日：2019-01-22
申请号：US15374114
申请日：2016-12-09
申请人： Cray, Inc.
发明人： Heidi Lynn Poxon , William Homer , David W. Oehmke , Luiz DeRose , Clayton D. Andreasen , Sanyam Mehta
IPC分类号： G06F12/02 , G06F12/08 , G06F8/41
摘要： A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.

4. 发明授权

US09674092B2 Congestion abatement in a network interconnect 有权
公开(公告)号：US09674092B2
公开(公告)日：2017-06-06
申请号：US15170277
申请日：2016-06-01
申请人： Cray Inc.
发明人： Edwin Lloyd Froese , Christopher Brian Johns , Aaron Forest Godfrey , Laurence S. Kaplan , Matthew Paul Kelly , Brent Thomas Shields
IPC分类号： H04L12/801 , H04L12/825 , H04L12/26 , H04L12/933 , H04L12/773
CPC分类号： H04L47/12 , H04L43/0852 , H04L45/60 , H04L47/11 , H04L47/25 , H04L47/263 , H04L49/10
摘要： A method and system for detecting congestion in a network of nodes, abating the network congestion, and identifying the cause of the network congestion is provided. A congestion detection system may comprise a detection system, an abatement system, and a causation system. The detection system monitors the performance of network components such as the network interface controllers and tiles of routers to determine whether the network is congested such that a delay in delivering packets becomes unacceptable. Upon detecting that the network is congested, an abatement system abates the congestion by limiting the rate at which packets are injected into the network from the nodes. Upon detecting that the network is congested, a causation system may identify the job that is executing on a node that is the cause of the network congestion.

5. 发明授权

US09672133B2 Systems and methods for debugging applications using dual code generation 有权
公开(公告)号：US09672133B2
公开(公告)日：2017-06-06
申请号：US14325463
申请日：2014-07-08
申请人： Cray Inc.
发明人： Robert Warren Moench , Robert Cushman Clark
IPC分类号： G06F9/44 , G06F11/36 , G06F9/45
CPC分类号： G06F11/362 , G06F8/443 , G06F11/3628
摘要： Systems and methods provide a debugger that debugs code using two versions of code, an optimized and a debuggable version of object code for subroutines, methods or functions. The debugger causes the appropriate version of the code to be executed depending on whether debug commands have been applied with respect to particular subroutines, methods or functions.

6. 发明授权

US09535804B2 Resiliency to memory failures in computer systems 有权
标题翻译：对计算机系统中的内存故障的弹性
公开(公告)号：US09535804B2
公开(公告)日：2017-01-03
申请号：US13476819
申请日：2012-05-21
申请人： Laurence S. Kaplan , Preston P. Briggs, III , Miles A. Ohlrich , Willard H. Leslie
发明人： Laurence S. Kaplan , Preston P. Briggs, III , Miles A. Ohlrich , Willard H. Leslie
IPC分类号： G06F11/14 , G06F11/20 , G06F11/10 , G06F11/08
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/067 , G06F3/0673 , G06F11/08 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1016 , G06F11/1068 , G06F11/1088 , G06F11/14 , G06F11/1402 , G06F11/1405 , G06F11/141 , G06F11/1479 , G06F11/1662 , G06F11/202 , G06F11/2023 , G06F11/2035 , G06F2201/805 , G06F2201/82
摘要： A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.
摘要翻译：弹性系统使用先前存储的纠错信息来检测和校正由计算系统的存储器系统报告的存储器错误。当程序将数据存储到存储器位置时，在计算系统上执行的弹性系统生成并存储纠错信息。当程序然后执行加载指令以从存储器位置检索数据时，如果没有存储器错误，则加载指令正常完成。然而，如果存在内存错误，则计算系统将控制权传给弹性系统（例如，经由陷阱）来处理存储器错误。弹性系统检索存储器位置的纠错信息并重新创建存储器位置的数据。弹性系统存储数据，就好像加载指令已经正常完成，并将控制权传给程序的下一条指令。

7. 发明授权

US08583898B2 System and method for managing processor-in-memory (PIM) operations 有权
标题翻译：用于管理处理器内存（PIM）操作的系统和方法
公开(公告)号：US08583898B2
公开(公告)日：2013-11-12
申请号：US12484062
申请日：2009-06-12
申请人： Terry D. Greyzck
发明人： Terry D. Greyzck
IPC分类号： G06F7/38 , G06K9/00
CPC分类号： G06F9/30036 , G06F9/30029 , G06F9/3004 , G06F9/30087 , G06F9/345 , G06F9/3455
摘要： A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for operations that are vectorizable. The vectorizable operations are examined to determine whether they should be executed at least in part in a vector atomic memory operation (AMO) functional unit attached to memory. If so, the compiled code includes vector AMO instructions.
摘要翻译：一种编译程序代码的系统和方法，其中所述程序代码包括对存储在计算机系统的存储器中的数据元素阵列的操作。对可向量化的操作扫描程序代码。检查可向量化的操作以确定它们是否至少部分地应用于附加到存储器的向量原子存储器操作（AMO）功能单元。如果是这样，编译代码包括向量AMO指令。

8. 发明申请

US20130229768A1 COMPUTER CABINETS HAVING PROGRESSIVE AIR VELOCITY COOLING SYSTEMS AND ASSOCIATED METHODS OF MANUFACTURE AND USE 审中-公开
标题翻译：具有先进空气冷却系统的计算机柜及相关的制造和使用方法
公开(公告)号：US20130229768A1
公开(公告)日：2013-09-05
申请号：US13864423
申请日：2013-04-17
申请人： CRAY INC.
发明人： Wade J. Doll
IPC分类号： G06F1/20
CPC分类号： G06F1/20 , H05K7/20736
摘要： Computer cabinets, such as supercomputer cabinets, having progressive air velocity cooling systems are described herein. In one embodiment, a computer cabinet includes an air mover positioned beneath a plurality of computer module compartments. The computer module compartments can be arranged in tiers with the computer modules in each successive tier being positioned closer together than the computer modules in the tier directly below. The computer cabinet can also include one or more shrouds, flow restrictors, and/or sidewalls that further control the direction and/or speed of the cooling air flow through the cabinet.
摘要翻译：这里描述了具有逐行风速冷却系统的计算机机柜，例如超级计算机机柜。在一个实施例中，计算机机柜包括位于多个计算机模块隔间下方的空气推动器。计算机模块隔间可以布置成层，每个连续层中的计算机模块被定位成比直接在下面的层中的计算机模块更靠近在一起。计算机机柜还可以包括一个或多个护罩，限流器和/或侧壁，其进一步控制通过机柜的冷却空气流的方向和/或速度。

9. 发明授权

US08413126B2 Scalar code reduction using shortest path routing 有权
标题翻译：使用最短路径路由的标量代码减少
公开(公告)号：US08413126B2
公开(公告)日：2013-04-02
申请号：US11763990
申请日：2007-06-15
申请人： James C. Beyer
发明人： James C. Beyer
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： This document discusses, among other things, a system and method computing the shortest path expression in a loop having a plurality of expressions. Candidate expressions in the loop are identified and partitioned into sets. A cost matrix is computed as a function of the sets. Paths are found through the cost matrix and, if there are cycles in the paths, the cycles are broken. One or more shortest path expressions are generated as a function of the paths and one or more of the expressions in the loop are replaced with the shortest path expressions.
摘要翻译：该文件尤其涉及一种在具有多个表达式的循环中计算最短路径表达式的系统和方法。循环中的候选表达式被识别并分割成集合。作为集合的函数计算成本矩阵。通过成本矩阵找到路径，如果路径中有循环，则循环被破坏。作为路径的函数生成一个或多个最短路径表达式，并且循环中的一个或多个表达式被最短路径表达式替换。

10. 发明申请

US20120311537A1 PERFORMANCE VISUALIZATION INCLUDING HIERARCHICAL DISPLAY OF PERFORMANCE DATA 审中-公开
标题翻译：性能可视化，包括性能数据的分层显示
公开(公告)号：US20120311537A1
公开(公告)日：2012-12-06
申请号：US13586174
申请日：2012-08-15
申请人： Luiz DeRose , Dean T. Johnson
发明人： Luiz DeRose , Dean T. Johnson
IPC分类号： G06F9/44
CPC分类号： G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F2201/865 , G06F2201/88 , G06F2201/885
摘要： Systems and methods provide a display indicating performance characteristics of a computer application. The display may include a call graph having nodes that represent subunits of the application. A first set of statistics for the subunit may be represented in the size or dimensions of the node. A second set of statistics may be displayed in the interior of the node. A third set of statistics may be displayed in response to selecting the node.
摘要翻译：系统和方法提供指示计算机应用的性能特征的显示。显示器可以包括具有表示应用的子单元的节点的调用图。子单元的第一组统计可以以节点的大小或尺寸表示。可以在节点的内部显示第二组统计信息。响应于选择节点，可以显示第三组统计信息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式