专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09195605B2 Data bus efficiency via cache line usurpation 有权
标题翻译：数据总线效率通过缓存线篡夺
公开(公告)号：US09195605B2
公开(公告)日：2015-11-24
申请号：US14687470
申请日：2015-04-15
申请人： Emulex Corporation
发明人： Steven Gerard LeMire , Vuong Cao Nguyen
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0888 , G06F12/0835 , G06F12/0893 , G06F2212/1024 , G06F2212/1044 , G06F2212/604 , G06F2212/6046 , G06F2212/608 , G06F2212/621
摘要： Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.
摘要翻译：本发明的实施例允许用户更有效地向主存储器分配高速缓冲存储器。处理器或用户分配高速缓冲存储器并将缓存存储器与主存储器位置相关联，但是抑制或绕过将主存储器数据读取到高速缓冲存储器中。本发明的一些实施例允许用户指定在给定时间分配多少高速缓存行。此外，本发明的实施例可以将高速缓存存储器初始化为指定的模式。高速缓冲存储器可以被归零或设置为某些期望的模式，例如所有模式。或者，用户可以通过处理器确定初始化模式。

2. 发明授权

US09183167B2 Enhanced I/O performance in a multi-processor system via interrupt affinity schemes 有权
标题翻译：通过中断关联方案在多处理器系统中提高I / O性能
公开(公告)号：US09183167B2
公开(公告)日：2015-11-10
申请号：US14087953
申请日：2013-11-22
申请人： EMULEX CORPORATION
发明人： Qiang Liu , Allen Russell Andrews , David Bradley Baldwin
IPC分类号： G06F3/00 , G06F13/24
CPC分类号： G06F13/32 , G06F3/061 , G06F3/0632 , G06F3/067 , G06F9/4812 , G06F9/5033 , G06F13/24
摘要： Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.
摘要翻译：这里公开了一种用于改善具有多个CPU的主机系统中的输入/输出（I / O）性能的方法。在这种方法下，提供了各种中断相关性方案，它们将多个处理器，中断和I / O通道相关联，用于发送中断，从而允许中断在多个I / O通道和处理器之间几乎均匀地加载。而且，可以通过将每个中断与其源处理器相关联的中断相关性方案（即，产生导致中断的I / O请求的处理器）来实现数据位置（“暖缓存”）。

3. 发明授权

US09146808B1 Soft error protection for content addressable memory 有权
标题翻译：内容可寻址存储器的软错误保护
公开(公告)号：US09146808B1
公开(公告)日：2015-09-29
申请号：US13749669
申请日：2013-01-24
申请人： EMULEX CORPORATION
发明人： Jim Butler , Sujith Arramreddy
IPC分类号： G11C29/00 , G06F11/10 , G11C15/04
CPC分类号： G06F12/0815 , G06F11/1064 , G06F11/1076 , G06F2212/1021 , G06F2212/621 , G11C15/00 , G11C15/04
摘要： In one embodiment of the invention, a method for protecting a content addressable memory is disclosed. The method includes storing a marker bit associated with each data block stored in a random access memory (RAM), states of the marker bit representing whether the data block was recently read from the RAM or recently written into the RAM; receiving a client address pointing to a starting address of a data block stored in the RAM; comparing the client address against one or more addresses stored in a content addressable memory (CAM) to determine a hit indicating the client address was stored in the CAM or a miss indicating the client address was not stored in the CAM; and in response to a miss, the method further includes checking a state of the marker bit associated with the data block pointed to by the client address.
摘要翻译：在本发明的一个实施例中，公开了一种用于保护内容可寻址存储器的方法。该方法包括存储与存储在随机存取存储器（RAM）中的每个数据块相关联的标记位，标记位的状态表示数据块是最近从RAM读取还是最近写入RAM中; 接收指向存储在RAM中的数据块的起始地址的客户地址; 将客户端地址与存储在内容可寻址存储器（CAM）中的一个或多个地址进行比较，以确定指示客户端地址的命中被存储在CAM中，或者指示客户端地址未存储在CAM中的未命中; 并且响应于未命中，该方法还包括检查与由客户端地址指向的数据块相关联的标记位的状态。

4. 发明授权

US09024878B2 Hardware cursor snooping 有权
标题翻译：硬件光标窥探
公开(公告)号：US09024878B2
公开(公告)日：2015-05-05
申请号：US12031056
申请日：2008-02-14
申请人： Dwarka Partani , Sujith Arramreddy , Wilfred A. Smith
发明人： Dwarka Partani , Sujith Arramreddy , Wilfred A. Smith
IPC分类号： G09G5/00 , G06F3/033 , G06F3/038
CPC分类号： G06F3/038 , G06F2203/0383
摘要： A feedback subsystem may be used to control the positioning of a local cursor of a display in response to receiving remote cursor movement information from a remote computer system. The feedback subsystem may send the remote cursor movement information to an operating system (OS) which may send local coordinate information to a graphics controller. Local coordinate information from the graphics controller may be used to compare with remote coordinate information received from the remote computer system. The feedback subsystem may repeatedly send the remote cursor movement information to the OS until it is determined that the local coordinate information from the graphics controller is consistent with the remote coordinate information received from the remote computer system.
摘要翻译：响应于从远程计算机系统接收远程光标移动信息，可以使用反馈子系统来控制显示器的本地光标的定位。反馈子系统可以将远程光标移动信息发送到操作系统（OS），操作系统可以向图形控制器发送局部坐标信息。来自图形控制器的局部坐标信息可用于与从远程计算机系统接收的远程坐标信息进行比较。反馈子系统可以重复地将远程光标移动信息发送到OS，直到确定来自图形控制器的局部坐标信息与从远程计算机系统接收的远程坐标信息一致。

5. 发明授权

US08989180B2 RoCE packet sequence acceleration 有权
公开(公告)号：US08989180B2
公开(公告)日：2015-03-24
申请号：US14206640
申请日：2014-03-12
申请人： Emulex Corporation
发明人： Parav Pandit , Masoodur Rahman , Kenny Meng-Hung Wu , Chaitanya Tumuluri
IPC分类号： H04L12/28 , G06F15/173 , G06F13/28 , H04L12/24
CPC分类号： H04L69/22 , G06F13/28 , G06F15/17331 , H04L12/28 , H04L41/06 , Y10T409/308736
摘要： A method, network device and system for remote direct memory access (RDMA) over Converged Ethernet (RoCE) packet sequence acceleration are disclosed. The network device comprises one or more functionality components for communicating with a host system. The host system is configured for implementing a first set of functionalities of a network communication protocol, such as RoCE. The one or more functionality components are also operable to implement a second set of functionalities of the network communication protocol.

6. 发明授权

US08892823B2 Data bus efficiency via cache line usurpation 有权
标题翻译：数据总线效率通过缓存线篡夺
公开(公告)号：US08892823B2
公开(公告)日：2014-11-18
申请号：US11966900
申请日：2007-12-28
申请人： Steven Gerard LeMire , Vuong Cao Nguyen
发明人： Steven Gerard LeMire , Vuong Cao Nguyen
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0888 , G06F12/0835 , G06F12/0893 , G06F2212/1024 , G06F2212/1044 , G06F2212/604 , G06F2212/6046 , G06F2212/608 , G06F2212/621
摘要： Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.
摘要翻译：本发明的实施例允许用户更有效地向主存储器分配高速缓冲存储器。处理器或用户分配高速缓冲存储器并将缓存存储器与主存储器位置相关联，但是抑制或绕过将主存储器数据读取到高速缓冲存储器中。本发明的一些实施例允许用户指定在给定时间分配多少高速缓存行。此外，本发明的实施例可以将高速缓存存储器初始化为指定的模式。高速缓冲存储器可以被归零或设置为某些期望的模式，例如所有模式。或者，用户可以通过处理器确定初始化模式。

7. 发明授权

US08705572B2 RoCE packet sequence acceleration 有权
标题翻译： RoCE包序列加速
公开(公告)号：US08705572B2
公开(公告)日：2014-04-22
申请号：US13103884
申请日：2011-05-09
申请人： Parav Pandit , Masoodur Rahman , Kenny Meng-Hung Wu , Chaitanya Tumuluri
发明人： Parav Pandit , Masoodur Rahman , Kenny Meng-Hung Wu , Chaitanya Tumuluri
IPC分类号： H04J3/24
CPC分类号： H04L69/22 , G06F13/28 , G06F15/17331 , H04L12/28 , H04L41/06 , Y10T409/308736
摘要： Disclosed herein are methods and apparatus for accelerating RoCE packet sequence transmission and reducing processing latency in received RoCE packets. Under the disclosed method, the RoCE protocol stack and RDMA verbs are implemented partially in the host software and partially in the adapter hardware, thereby providing a better balance between simplifying the adapter configuration and maximizing the host processing efficiency. Particularly, the adapter implemented with partial RoCE offload is able to perform a few major functionalities under the RoCE protocol, such as offloading a complete RoCE packet sequence for transmission, building individual packets out of the RoCE packet sequence and performing Invariant CRC calculation, insertion, validation and removal thereof.
摘要翻译：这里公开了用于加速RoCE分组序列传输并减少接收的RoCE分组中的处理等待时间的方法和装置。在所公开的方法下，RoCE协议栈和RDMA动词部分地在主机软件中实现，部分实现在适配器硬件中，从而在简化适配器配置和最大化主机处理效率之间提供更好的平衡。特别地，用部分RoCE卸载实现的适配器能够在RoCE协议下执行几个主要功能，例如卸载用于传输的完整RoCE分组序列，从RoCE分组序列构建各个分组并执行不变CRC计算，插入，验证和删除它们。

8. 发明申请

US20040267982A1 Read/write command buffer pool resource management using read-path prediction of future resources 失效
标题翻译：读/写命令缓冲池资源管理使用对未来资源的预读
公开(公告)号：US20040267982A1
公开(公告)日：2004-12-30
申请号：US10609291
申请日：2003-06-27
申请人： EMULEX CORPORATION
发明人： Thomas Patrick Jackson , Curtis Edward Nottberg , David Robert Wiley , Marc Timothy Jones
IPC分类号： G06F013/14
CPC分类号： G06F13/385
摘要： A method for managing read and write data congestion in a system for executing write and read data commands and having a buffer pool of blocks for temporarily storing read and write data is disclosed. Management of the buffer pool and the initiation of read and write commands ensures that free blocks are available to temporarily store read data arriving at a host bus adapter (HBA). If the currently available blocks would be substantially consumed by the total outstanding inbound read data requested, no more write data commands will be initiated. As inbound read data is received into the buffer pool and subsequently transferred out of the buffer pool to the initiator device, the blocks in the buffer pool are freed up. When the read data transfer is completed and sufficient buffer resources have been freed up, read and write data commands may resume.

9. 发明申请

US20040267692A1 Sparse and non-sparse data management method and system 有权
标题翻译：稀疏和非稀疏的数据管理方法和系统
公开(公告)号：US20040267692A1
公开(公告)日：2004-12-30
申请号：US10609289
申请日：2003-06-27
申请人： EMULEX CORPORATION
发明人： M. Tim Jones , Scott Smallwood
IPC分类号： G06F007/00
CPC分类号： H04L67/1097 , H04L1/1829 , H04L69/16 , H04L69/163 , H04L69/324 , Y10S707/99945 , Y10S707/99948
摘要： A method and system for tracking data packets that utilizes a tree data structure with a recursive pruning algorithm that collapses the branches of the tree that represent contiguous ranges or regions to maintain a minimally optimum memory size. Each contiguous region is identified by a node, which includes the start and end range of packets. Each node further includes left and right pointer elements, which point to adjacent lower and higher nodes, respectively. When a packet sequence number is not contiguous with any other sequence numbers previously received, a new node is created that contains only a single value range. When a new packet is received that has a contiguous sequence number (i.e., immediately preceding or succeeding sequence number), the original node is updated so as to reflect the new contiguous range. Additionally, if this new contiguous range is contiguous with another node's range, the two nodes are nullcollapsednull into a new single node containing the new expanded contiguous range. Furthermore, the algorithm can quickly and efficiently determine whether there are any missing packets by simply determining if there is only a single node remaining after a designated nulllast packetnull has been received.

10. 发明申请

US20010028657A1 Automatic isolation in loops 失效
公开(公告)号：US20010028657A1
公开(公告)日：2001-10-11
申请号：US09849102
申请日：2001-05-04
申请人： Emulex Corporation
发明人： David Brewer , Karl M. Henson , Hossein Hashemi , David Baldwin
IPC分类号： H04J001/16
CPC分类号： H04L12/437 , H04B10/038
摘要： A loop network hub port with an automatic bypass feature. The automatic bypass feature causes the hub port to enter a bypass mode upon detection of a specified loop failure initialization sequence from a node port attached to the hub port. The hub port does not propagate loop failure initialization data generated by the attached node port upon the failure of a data channel from the hub port to the node port. The hub port replaces loop failure initialization data received from the node port with buffer data and conceals the node port failure from the remainder of the loop. Upon detection of the loop failure initialization sequence received from the attached node port, the hub port enters a bypass mode and maintains that bypass mode until a recovery sequence is received from the node port. At that point, the hub port reinserts the node port into the loop.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式