会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明申请
    • Technique for Stable Processing of Thin/Fragile Substrates
    • 薄/脆性基板的稳定加工技术
    • US20080315345A1
    • 2008-12-25
    • US12203995
    • 2008-09-04
    • Robin WilsonConor BroganHugh J. GriffinCormac MacNamara
    • Robin WilsonConor BroganHugh J. GriffinCormac MacNamara
    • H01L21/302H01L23/58
    • H01L21/78
    • A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.
    • 绝缘体上半导体(SOI)晶片包括具有彼此相对的第一和第二主表面的半导体衬底。 电介质层设置在半导体衬底的第一主表面的至少一部分上。 器件层具有第一主表面和第二主表面。 器件层的第二主表面设置在与半导体衬底相对的电介质层的表面上。 在设备层的第一主表面上限定多个预期的管芯区域。 多个预期的模具区域彼此分离。 多个裸片存取沟槽从第二主表面形成在半导体衬底中。 多个管芯存取沟槽中的每一个通常设置在多个预期管芯区域中的至少一个相应的一个的下方。
    • 3. 发明申请
    • BONDED-WAFER SUPERJUNCTION SEMICONDUCTOR DEVICE
    • 粘结超声波半导体器件
    • US20080315247A1
    • 2008-12-25
    • US12191035
    • 2008-08-13
    • Conor BroganCormac MacNamaraHugh J. GriffinRobin Wilson
    • Conor BroganCormac MacNamaraHugh J. GriffinRobin Wilson
    • H01L29/00
    • H01L21/2007H01L21/76251H01L29/0634H01L29/66143H01L29/872
    • A bonded-wafer semiconductor device includes a semiconductor substrate, a buried oxide layer disposed on a first main surface of the semiconductor substrate and a multi-layer device stack. The multi-layer device stack includes a first device layer of a first conductivity disposed on the buried oxide layer, a second device layer of a second conductivity disposed on the first device layer, a third device layer of the first conductivity disposed on the second device layer and a fourth device layer of the second conductivity disposed on the third device layer. A trench is formed in the multi-layer device stack. A mesa is defined by the trench. The mesa has first and second sidewalls. A first anode/cathode layer is disposed on a first sidewall of the multi-layer device stack, and a second anode/cathode layer is disposed on the second sidewall of the multi-layer device stack.
    • 接合晶片半导体器件包括半导体衬底,设置在半导体衬底的第一主表面上的掩埋氧化物层和多层器件堆叠。 多层器件堆叠包括设置在掩埋氧化物层上的第一导电体的第一器件层,设置在第一器件层上的第二导电体的第二器件层,设置在第二器件上的第一导电体的第三器件层 层和设置在第三器件层上的第二导电体的第四器件层。 在多层器件堆叠中形成沟槽。 台面由沟槽定义。 台面具有第一和第二侧壁。 第一阳极/阴极层设置在多层器件堆叠的第一侧壁上,第二阳极/阴极层设置在多层器件堆叠的第二侧壁上。
    • 7. 发明申请
    • Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes
    • 使用隔离扩散作为相邻光电二极管之间的串扰抑制剂的光电检测器阵列
    • US20070085117A1
    • 2007-04-19
    • US11548546
    • 2006-10-11
    • Robin WilsonConor BroganHugh GriffinCormac MacNamara
    • Robin WilsonConor BroganHugh GriffinCormac MacNamara
    • H01L31/113
    • H01L27/14683H01L27/1463
    • A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate.
    • 光电检测器阵列包括具有相对的第一和第二主表面的半导体衬底,靠近第一主表面的第一掺杂浓度的第一层和靠近第二主表面的第二掺杂浓度的第二层。 光电检测器包括形成在第一主表面中的至少一个导电通孔和靠近第一主表面和至少一个导电通孔的阳极/阴极区域。 通孔延伸到第二主表面。 导电通孔通过第一电介质材料与半导体衬底隔离。 阳极/阴极区域是与第一导电性相反的第二导电性。 光电检测器包括形成在第一主表面中并延伸穿过半导体衬底的第一层的至少第二层半导体衬底的第三掺杂浓度的掺杂隔离区。
    • 9. 发明申请
    • PHOTODETECTOR ARRAY USING ISOLATION DIFFUSIONS AS CROSSTALK INHIBITORS BETWEEN ADJACENT PHOTODIODES
    • 使用隔离扩散剂作为相容光刻胶之间的波形抑制剂的光电子阵列
    • US20080315269A1
    • 2008-12-25
    • US12204371
    • 2008-09-04
    • Robin WilsonConor BroganHugh J. GriffinCormac MacNamara
    • Robin WilsonConor BroganHugh J. GriffinCormac MacNamara
    • H01L31/113
    • H01L27/14683H01L27/1463
    • A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate.
    • 光电检测器阵列包括具有相对的第一和第二主表面的半导体衬底,靠近第一主表面的第一掺杂浓度的第一层和靠近第二主表面的第二掺杂浓度的第二层。 光电检测器包括形成在第一主表面中的至少一个导电通孔和靠近第一主表面和至少一个导电通孔的阳极/阴极区域。 通孔延伸到第二主表面。 导电通孔通过第一电介质材料与半导体衬底隔离。 阳极/阴极区域是与第一导电性相反的第二导电性。 光电检测器包括形成在第一主表面中并延伸穿过半导体衬底的第一层的至少第二层半导体衬底的第三掺杂浓度的掺杂隔离区。