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    • 2. 发明授权
    • Electrical connectivity for circuit applications
    • 电路连接用于电路应用
    • US09171743B2
    • 2015-10-27
    • US14045949
    • 2013-10-04
    • Donald J. DesbiensGary D. PolhemusRobert T. Carroll
    • Donald J. DesbiensGary D. PolhemusRobert T. Carroll
    • H01L23/48H01L21/50H01L23/482H01L23/495H01L25/07
    • H01L21/50H01L23/4824H01L23/49562H01L25/072H01L2224/16245H01L2924/1305H01L2924/00
    • According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
    • 根据这里的示例性配置,引线框架包括第一导电条,第二导电条和基本相邻并基本上彼此平行设置的第三导电条。 半导体芯片衬底包括与第二阵列开关电路相邻并平行设置的第一开关电路阵列。 第一阵列的开关电路中的源节点被设置为基本上与第二阵列的开关电路中的源节点相邻并且基本上平行。 当半导体芯片和引线框架装置组合以形成电路封装时,电路封装件中的半导体芯片与导电条之间的连接接口将第一阵列的开关电路中的每个源节点与多个源节点 在第二阵列的开关电路中到引线框装置中的公共导电条。
    • 3. 发明授权
    • Semiconductor package with integrated passives and method for fabricating same
    • 具有集成无源的半导体封装及其制造方法
    • US09159679B2
    • 2015-10-13
    • US12584420
    • 2009-09-03
    • Michael A. Briere
    • Michael A. Briere
    • H01L23/64H01L23/522
    • H01L23/642H01L23/5223H01L23/5227H01L23/645H01L2924/0002H01L2924/00
    • According to one disclosed embodiment, a semiconductor package for integrated passives and a semiconductor device comprises a high permeability structure formed over a surface of the semiconductor package and surrounding a contact body of the semiconductor package, the contact body being connected to an output of the semiconductor device. The contact body can be, for example, a solder bump. The high permeability structure causes a substantial increase in inductance of the contact body so as to form an increased inductance inductor coupled to the output of the semiconductor device. In one embodiment, the semiconductor package further comprises a blanket insulator formed over the high permeability structure, and a capacitor stack formed over the blanket insulator. In one embodiment, the semiconductor device comprises a group III-V power semiconductor device.
    • 根据一个公开的实施例,用于集成无源的半导体封装和半导体器件包括形成在半导体封装的表面上并围绕半导体封装的接触体的高磁导率结构,该接触体连接到半导体的输出端 设备。 接触体可以是例如焊料凸块。 高导磁率结构导致接触体的电感的显着增加,从而形成耦合到半导体器件的输出的增加的电感电感器。 在一个实施例中,半导体封装还包括形成在高导磁率结构上的覆盖绝缘体,以及形成在覆盖绝缘体上的电容器堆叠。 在一个实施例中,半导体器件包括III-V族功率半导体器件。