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1. 发明申请

US20130168746A1 SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US20130168746A1
公开(公告)日：2013-07-04
申请号：US13618004
申请日：2012-09-14
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/785
摘要： A semiconductor device manufacturing method includes providing a mask on a semiconductor member. The method further includes providing a dummy element to cover a portion of the mask that overlaps a first portion of the semiconductor member and to cover a second portion of the semiconductor member. The method further includes removing a third portion of the semiconductor member, which has not been covered by the mask or the dummy element. The method further includes providing a silicon compound that contacts the first portion of the semiconductor member. The method further includes removing the dummy element to expose and to remove the second portion of the semiconductor member. The method further includes forming a gate structure that overlaps the first portion of the semiconductor member. The first portion of the semiconductor member is used as a channel region and is supported by the silicon compound.
摘要翻译：半导体器件制造方法包括在半导体部件上设置掩模。该方法还包括提供虚拟元件以覆盖与半导体部件的第一部分重叠并覆盖半导体部件的第二部分的掩模的一部分。该方法还包括去除未被掩模或虚拟元件覆盖的半导体部件的第三部分。该方法还包括提供接触半导体部件的第一部分的硅化合物。该方法还包括去除虚设元件以暴露并移除半导体部件的第二部分。该方法还包括形成与半导体部件的第一部分重叠的栅极结构。半导体部件的第一部分用作沟道区域并由硅化合物支撑。

2. 发明申请

US20130134488A1 Semiconductor Device and Manufacturing Method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130134488A1
公开(公告)日：2013-05-30
申请号：US13552446
申请日：2012-07-18
申请人： Mieno Fumitake
发明人： Mieno Fumitake
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/098 , H01L21/26586 , H01L21/823821 , H01L27/0924 , H01L29/0657 , H01L29/66901 , H01L29/785 , H01L29/808
摘要： A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.
摘要翻译：提供了一种半导体器件及其制造方法。翅片半导体器件包括形成在衬底上的翅片和形成在衬底上并围绕翅片的绝缘材料层。翅片具有半导体层，该半导体层具有源极区部分和漏极区域部分。翅片包括第一通道控制区域，第二通道控制区域和两个通道控制区域之间的通道区域，它们都位于源极区域部分和漏极区域部分之间。两个通道控制区域可以具有与通道区域不同的导电类型。

3. 发明授权

US09312378B2 Transistor device 有权
标题翻译：晶体管器件
公开(公告)号：US09312378B2
公开(公告)日：2016-04-12
申请号：US14795820
申请日：2015-07-09
申请人： Semiconductor Manufacturing International Corp.
发明人： Jianguang Chang
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423 , H01L29/49 , H01L29/792 , H01L21/28 , H01L29/51
CPC分类号： H01L29/78 , H01L21/28202 , H01L29/42364 , H01L29/4916 , H01L29/513 , H01L29/518 , H01L29/66477 , H01L29/66575 , H01L29/66833 , H01L29/792
摘要： Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption.
摘要翻译：各种实施例提供晶体管和制造方法。示例性晶体管可以包括设置在栅极电介质层和栅极电极层之间的氮化硅层。氮化硅层可以具有与栅极电介质层接触的第一表面和与栅极电极层接触的第二表面。第二表面可以包括具有高于第一表面的浓度的硅原子。可以在栅极电极层，氮化硅层和栅极介电层中的每一个的侧壁上的半导体衬底上形成侧壁间隔物。所公开的晶体管可以具有降低的导通电压，同时具有降低的功耗。

4. 发明授权

US09190282B2 High-K dielectric layer based semiconductor structures and fabrication process thereof 有权
标题翻译：基于高K电介质层的半导体结构及其制造方法
公开(公告)号：US09190282B2
公开(公告)日：2015-11-17
申请号：US13662535
申请日：2012-10-28
申请人： Aileen Li , Jinghua Ni
发明人： Aileen Li , Jinghua Ni
IPC分类号： H01L21/8242 , H01L21/28 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28202 , H01L29/518 , H01L29/78
摘要： A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming a first dielectric layer on a surface of the semiconductor substrate based on a first-type oxidation, and forming a high-K dielectric layer on a surface of the first dielectric layer. The method also includes performing a first thermal annealing process to remove the first dielectric layer between the semiconductor substrate and the high-K dielectric layer such that the high-K dielectric layer is on the surface of the semiconductor substrate. Further, the method includes performing a second thermal annealing process to form a second dielectric layer on the surface of the semiconductor substrate between the semiconductor substrate and the high-K dielectric layer, based on a second-type oxidation different from the first-type oxidation, such that high-K dielectric layer is on the second dielectric layer instead of the first dielectric layer.
摘要翻译：公开了制造半导体结构的方法。该方法包括提供半导体衬底，基于第一类型氧化在半导体衬底的表面上形成第一电介质层，以及在第一电介质层的表面上形成高K电介质层。该方法还包括执行第一热退火处理以去除半导体衬底和高K电介质层之间的第一介电层，使得高K电介质层在半导体衬底的表面上。此外，该方法包括进行第二热退火处理以在半导体衬底和高K电介质层之间的半导体衬底的表面上形成第二介电层，基于与第一类型氧化不同的第二类型氧化使得高K电介质层位于第二介电层上而不是第一介电层。

5. 发明授权

US09117907B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09117907B2
公开(公告)日：2015-08-25
申请号：US14607613
申请日：2015-01-28
申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.
发明人： Zhongshan Hong
IPC分类号： H01L27/12 , H01L29/78 , H01L21/36 , H01L29/06 , H01L29/10 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/1033 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/495 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66795 , H01L29/78
摘要： A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer.
摘要翻译：公开了半导体器件的制造工艺。该方法包括提供半导体衬底，其具有形成在半导体衬底上的第一绝缘层和形成在第一绝缘层的表面上的鳍，以及在鳍的侧壁上形成完全耗尽的半导体层，以及完全耗尽的半导体层具有不同于翅片的材料。该方法还包括形成覆盖完全耗尽的半导体层的第二绝缘层，以及去除鳍以形成暴露完全耗尽的半导体层的侧壁的开口。此外，该方法包括在完全耗尽的半导体层的侧壁的一部分上形成栅极电介质层，使得全部耗尽的半导体层的侧壁的一部分形成半导体器件的沟道区，并且形成栅电极层覆盖栅介电层。

6. 发明授权

US09112020B2 Transistor device 有权
标题翻译：晶体管器件
公开(公告)号：US09112020B2
公开(公告)日：2015-08-18
申请号：US14607741
申请日：2015-01-28
申请人： Semiconductor Manufacturing International Corp
发明人： Neil Zhao , Mieno Fumitake
IPC分类号： H01L29/15 , H01L29/78 , H01L29/16 , H01L29/161 , H01L29/165
CPC分类号： H01L29/78 , H01L21/26506 , H01L21/26566 , H01L29/1054 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/267 , H01L29/66431 , H01L29/665 , H01L29/66575 , Y10S438/931
摘要： Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.
摘要翻译：各种实施例提供晶体管器件和制造方法。具有改善的载流子迁移率的示例性晶体管器件可以通过首先在半导体衬底上形成约束层以将从半导体衬底扩散的杂质离子限制到限制层来形成。可以在约束层上形成外延硅层，随后在外延硅层上形成栅极结构。外延硅层的一部分可以用作固有沟道区。源极区域和漏极区域可以形成在每个外延硅层，约束层和半导体衬底的部分中。

7. 发明授权

US08975642B2 Transistor device and fabrication method 有权
标题翻译：晶体管器件及其制造方法
公开(公告)号：US08975642B2
公开(公告)日：2015-03-10
申请号：US13686163
申请日：2012-11-27
申请人： Neil Zhao , Mieno Fumitake
发明人： Neil Zhao , Mieno Fumitake
IPC分类号： H01L29/15 , H01L29/78 , H01L29/66 , H01L29/16 , H01L29/267 , H01L29/10 , H01L29/161 , H01L29/165 , H01L21/265
CPC分类号： H01L29/78 , H01L21/26506 , H01L21/26566 , H01L29/1054 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/267 , H01L29/66431 , H01L29/665 , H01L29/66575 , Y10S438/931
摘要： Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.
摘要翻译：各种实施例提供晶体管器件和制造方法。具有改善的载流子迁移率的示例性晶体管器件可以通过首先在半导体衬底上形成约束层以将从半导体衬底扩散的杂质离子限制到限制层来形成。可以在约束层上形成外延硅层，随后在外延硅层上形成栅极结构。外延硅层的一部分可以用作固有沟道区。源极区域和漏极区域可以形成在每个外延硅层，约束层和半导体衬底的部分中。

8. 发明授权

US08917489B2 Apparatus and method for holding a wafer 有权
标题翻译：用于保持晶片的装置和方法
公开(公告)号：US08917489B2
公开(公告)日：2014-12-23
申请号：US13649576
申请日：2012-10-11
申请人： Semiconductor Manufacturing International Corp.
发明人： Emily Shu
IPC分类号： H01T23/00 , H01L21/683 , H01L21/67
CPC分类号： H01L21/6833 , H01L21/67288
摘要： An apparatus and a method for holding a wafer are provided in this disclosure. The wafer holding apparatus includes: an electrostatic chuck, the electrostatic chuck having a plurality of concentric zones; a plurality of power supply units, each adapted for applying a voltage to one of the zones of the electrostatic chuck independently; and a control unit, adapted for controlling each of the power supply units independently to start or stop applying the voltage to a corresponding zone of the electrostatic chuck. Surface flatness is improved when the wafer is chucked on the wafer holding apparatus according to the disclosure, and the risk of particle contamination can be reduced when the wafer is flattened and gets back into warpage from flatness.
摘要翻译：本公开提供了一种用于保持晶片的装置和方法。晶片保持装置包括：静电卡盘，该静电卡盘具有多个同心区域; 多个电源单元，各自适于独立地向静电卡盘的一个区域施加电压; 以及控制单元，适于独立地控制每个电源单元以启动或停止将电压施加到静电卡盘的相应区域。当晶片被夹在根据本公开的晶片保持装置上时，表面平坦性得到改善，并且当晶片扁平化并从平坦度恢复到翘曲状态时，可以减小颗粒污染的风险。

9. 发明授权

US08901675B2 CMOS devices and fabrication method 有权
标题翻译： CMOS器件及制作方法
公开(公告)号：US08901675B2
公开(公告)日：2014-12-02
申请号：US13714452
申请日：2012-12-14
申请人： Semiconductor Manufacturing International Corp.
发明人： Weihai Bu , Wenbo Wang , Shaofeng Yu , Hanming Wu
IPC分类号： H01L21/70 , H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/8238 , H01L21/823842
摘要： A method is provided for fabricating a CMOS device. The method includes providing a semiconductor substrate having a first active region and a second active region. The method also includes forming a first trench on the first active region using a first barrier layer and a second substitute gate electrode layer to protect a gate region on the second active region, followed by forming a first work function layer and a first metal gate in the first trench. Further, the method includes forming a second trench on the second active region using a second barrier layer to protect the first metal gate structure, followed by forming a second work function layer and a second metal gate in the second trench.
摘要翻译：提供了一种制造CMOS器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底。该方法还包括使用第一势垒层和第二替代栅极电极层在第一有源区上形成第一沟槽，以保护第二有源区上的栅极区，随后在第一有源区中形成第一功函数层和第一金属栅极第一个沟槽。此外，该方法包括使用第二阻挡层在第二有源区上形成第二沟槽，以保护第一金属栅极结构，随后在第二沟槽中形成第二功函数层和第二金属栅极。

10. 发明授权

US08802523B2 CMOS device and fabrication method 有权
标题翻译： CMOS器件及其制造方法
公开(公告)号：US08802523B2
公开(公告)日：2014-08-12
申请号：US13675216
申请日：2012-11-13
申请人： Zhongshan Hong
发明人： Zhongshan Hong
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/8238 , H01L21/26506 , H01L21/823842 , H01L27/092 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/78 , H01L29/7848
摘要： Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and fabrication methods. An exemplary CMOS device can be formed by providing a first dummy gate over a semiconductor substrate in a first region, providing a second dummy gate over the semiconductor substrate in a second region, and amorphizing a surface portion of the first dummy gate to form a first amorphous silicon layer. The first amorphous silicon layer can be used to protect the first dummy gate in the first region, when a second opening is formed in the second region by wet etching at least the second dummy gate. A second metal gate can then be formed in the second opening, followed by removing the first amorphous silicon layer and at least the first dummy gate to form a first opening in the first region. A first metal gate can be formed in the first opening.
摘要翻译：各种实施例提供互补的金属氧化物半导体（CMOS）器件和制造方法。可以通过在第一区域中的半导体衬底上提供第一虚拟栅极来形成示例性CMOS器件，在第二区域中在半导体衬底上提供第二虚拟栅极，并且使第一虚拟栅极的表面部分非晶化，以形成第一非晶硅层。当通过至少第二虚拟栅极湿蚀刻在第二区域中形成第二开口时，第一非晶硅层可用于保护第一区域中的第一伪栅极。然后可以在第二开口中形成第二金属栅极，随后去除第一非晶硅层和至少第一伪栅极以在第一区域中形成第一开口。可以在第一开口中形成第一金属栅极。

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