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1. 发明申请

US20160079091A1 METHOD FOR PRODUCING SUBSTRATE FOR MOUNTING SEMICONDUCTOR ELEMENT 有权
标题翻译：生产用于安装半导体元件的基板的方法
公开(公告)号：US20160079091A1
公开(公告)日：2016-03-17
申请号：US14786831
申请日：2014-03-11
申请人： SH MATERIALS CO., LTD.
发明人： Kaoru HISHIKI , Shunichi KIDOGUCHI , Hiroki NAKAYAMA
IPC分类号： H01L21/48
CPC分类号： H01L21/4825 , H01L21/4828 , H01L21/4846 , H01L23/49866 , H01L2924/0002 , H01L2924/00
摘要： [Object] To provide a substrate for semiconductor element mount that makes it possible to stably produce, in a highly mass-productive manner, surface-mount type semiconductor devices.[Solution] The method for producing substrate for semiconductor element mount is characterized by sequentially passing through the following processes (1) to (7): (1) preparing a base substrate 3 having, on a first metal layer 1, a second metal layer 2 through which a metal layer for instrumentation is hardly diffusible; (2) forming a patterned resist mask layer 4 on the second metal layer of the base substrate; (3) placing a surface of the second metal layer remaining uncovered off the resist mask layer under reprocessing treatment, to form a reprocessed surface; (4) providing the reprocessed surface of the base substrate with an organic film that controls adhesion between the metal layer for instrumentation and the reprocessed surface by a liquid agent containing a component that shows the nature of amphoteric surfactant; (5) forming the metal layer for instrumentation on the reprocessed surface of the base substrate via the organic film; (6) forming, on the metal layer for instrumentation, a semiconductor element mount portion and an electrode terminal portion by electroforming; and (7) removing the resist mask from the second metal layer of the base substrate.
摘要翻译：本发明提供一种半导体元件安装用基板，能够以高质量的方式稳定地制造表面安装型半导体元件。 [解决方案]半导体元件安装用基板的制造方法的特征在于，依次通过以下工序（1）〜（7）：（1）制备在第一金属层1上具有第二金属层 2，用于仪器的金属层难以扩散; （2）在基底基板的第二金属层上形成图案化的抗蚀剂掩模层4; （3）在再处理处理下将第二金属层的表面保留未被覆盖在抗蚀剂掩模层上，形成再加工表面; （4）通过含有显示两性表面活性剂性质的组分的液体试剂，提供控制用于仪器的金属层和后处理表面之间的粘合的有机膜的基底衬底的后处理表面; （5）通过有机膜在基底基板的后处理表面上形成用于仪器的金属层; （6）在用于仪表的金属层上通过电铸形成半导体元件安装部分和电极端子部分; 和（7）从基底衬底的第二金属层去除抗蚀剂掩模。

2. 发明授权

US09870930B2 Method for producing substrate for mounting semiconductor element 有权
公开(公告)号：US09870930B2
公开(公告)日：2018-01-16
申请号：US14786831
申请日：2014-03-11
申请人： SH MATERIALS CO., LTD.
发明人： Kaoru Hishiki , Shunichi Kidoguchi , Hiroki Nakayama
IPC分类号： H01L21/48 , H01L23/498
CPC分类号： H01L21/4825 , H01L21/4828 , H01L21/4846 , H01L23/49866 , H01L2924/0002 , H01L2924/00
摘要： Methods for producing a substrate for semiconductor element mounts are provided. A base substrate can be prepared having on a first metal layer, a second metal layer through which a metal layer for instrumentation is hardly diffusible. A patterned resist mask layer on the second metal layer can be formed. A surface of the second metal layer under reprocessing treatment can form a reprocessed surface which can be provided with an organic film that controls adhesion between the metal layer for instrumentation and the reprocessed surface by a liquid agent containing a component that shows the nature of amphoteric surfactant. The metal layer for instrumentation can be formed on the reprocessed surface via the organic film. A semiconductor element mount portion and an electrode terminal portion can be electroformed on the metal layer for instrumentation. The resist mask from the second metal layer of the base substrate may be removed.

3. 发明授权

US09735096B1 Lead frame and method for manufacturing the same 有权
公开(公告)号：US09735096B1
公开(公告)日：2017-08-15
申请号：US15504404
申请日：2015-07-30
申请人： SH MATERIALS CO., LTD.
发明人： Kaoru Hishiki , Yasuo Toyoshi
IPC分类号： H01L23/495 , H01L33/62 , H01L21/48
CPC分类号： H01L23/49582 , H01L21/4828 , H01L23/49503 , H01L23/49548 , H01L33/62
摘要： A metal plate 1 to be a lead frame has a plating with Sn or Zn or a plating with various alloys containing these metals only on the side faces and half-etched faces 6, and a noble metal plating layer formed on the front surface as a surface on which a semiconductor device is to be mounted.

4. 发明授权

US09691689B2 Lead frame for mounting semiconductor element and method for manufacturing the same 有权
公开(公告)号：US09691689B2
公开(公告)日：2017-06-27
申请号：US14777844
申请日：2014-03-18
申请人： SH MATERIALS CO., LTD.
发明人： Ryouichi Yoshimoto , Ryohei Yamashita
IPC分类号： H01L23/495 , H01L21/48
CPC分类号： H01L23/49548 , H01L21/4828 , H01L23/49503 , H01L23/4952 , H01L23/49541 , H01L23/49582 , H01L2924/0002 , H01L2924/00
摘要： A lead frame for mounting semiconductor element includes a protrusion that is horizontally projects from edges of the upper and lower surfaces of a semiconductor-mounting part or a terminal part of the lead frame and that is provided on a lateral side of at least one of the semiconductor-mounting part or the terminal part of the lead frame, wherein the top end of the protrusion is substantially flat or the profile of the cross section of the top end is arc-shaped, and the top end of the protrusion is thick.

5. 发明授权

US09583422B2 Lead frame 有权
标题翻译：引线架
公开(公告)号：US09583422B2
公开(公告)日：2017-02-28
申请号：US15002640
申请日：2016-01-21
申请人： SH MATERIALS CO., LTD. , NICHIA CORPORATION
发明人： Katsuyuki Doumae , Yoshio Ichihara , Shimpei Sasaoka
IPC分类号： H01L23/495
CPC分类号： H01L23/49544 , H01L23/49503 , H01L23/49541 , H01L2924/0002 , H01L2924/00
摘要： A lead frame, as one product unit in a multi-row lead frame sharing a partition frame among other lead frames, has a non-mirrorsymmetric pad region and at least one terminal region arranged inside and held to a rectangular outer frame region, which is a part of the partition frame and forms a boundary of the lead frame as a product unit, via respective suspension leads. Only two suspension leads hold the non-mirrorsymmetric pad region to the outer frame region as extending from opposite sides of the outer frame region to the non-mirrorsymmetric pad region, respectively. This structure decreases stress resulting from holding of the non-mirrorsymmetric pad region to the outer frame region and thus can prevent the outer frame region from deformation without widened connecting bars or dambars, which form the outer frame region.
摘要翻译：作为在其他引线框架中共享分隔框架的多行引线框架中的一个产品单元的引线框架具有非反射对称焊盘区域和布置在内部并保持在矩形外框区域中的至少一个端子区域，其中，分隔框架的一部分，并通过各自的悬挂引线形成作为产品单元的引线框架的边界。只有两个悬挂引线将非反射对称焊盘区域保持到外框区域，分别从外框区域的相对侧延伸到非反射对称焊盘区域。这种结构减小了由于将非反射对称垫区域保持在外框区域而产生的应力，从而可防止外框区域变形，而不会形成外框架区域的加宽的连接条或堰。

6. 发明申请

US20160300732A1 METHOD FOR PRODUCING SUBSTRATE FOR SEMICONDUCTOR ELEMENT MOUNTING 审中-公开
标题翻译：用于生产半导体元件安装衬底的方法
公开(公告)号：US20160300732A1
公开(公告)日：2016-10-13
申请号：US14777834
申请日：2014-03-11
申请人： SH MATERIALS CO., LTD.
发明人： Shigeru HOSOMOMI
IPC分类号： H01L21/48 , G03F7/20 , G03F7/32 , H01L21/56
CPC分类号： H01L21/4832 , G03F7/2022 , G03F7/32 , H01L21/4821 , H01L21/4825 , H01L21/4846 , H01L21/565 , H01L23/49548 , H01L23/49866 , H01L23/49894 , H01L2924/0002 , H01L2924/00
摘要： A process of forming, on a surface of the substrate a plurality of resist layers made of two kinds of dry film resist that differ in main peak wavelength in spectral photosensitivity. An exposure process of selectively exposing and affecting a particular resist layer in accordance with a first pattern upon using a first exposure mask overlaid on the plurality of resist layers. A second exposure process of exposing another resist layer in accordance with a second pattern upon using a second exposure mask overlaid on the plurality of resist layers. Partially uncovering the surface of the substrate by removing unexposed portions of the plurality of resist layers, to form a resist mask having an aperture. Finally, forming a coat layer by plating a portion of the substrate where the surface thereof is uncovered; and a process of removing the resist mask.
摘要翻译：在基板的表面上形成由光谱光敏性的主峰波长不同的两种干膜抗蚀剂制成的多个抗蚀剂层的工序。在使用覆盖在多个抗蚀剂层上的第一曝光掩模时，根据第一图案选择性地曝光和影响特定抗蚀剂层的曝光过程。在使用覆盖在多个抗蚀剂层上的第二曝光掩模时，根据第二图案曝光另一抗蚀剂层的第二曝光工艺。通过去除多个抗蚀剂层的未曝光部分来部分地露出衬底的表面，以形成具有孔径的抗蚀剂掩模。最后，通过镀覆其表面未被覆盖的基板的一部分来形成涂层; 以及除去抗蚀剂掩模的工序。

7. 发明授权

US09735106B2 Semiconductor lead frame, semiconductor package, and manufacturing method thereof 有权
公开(公告)号：US09735106B2
公开(公告)日：2017-08-15
申请号：US15156730
申请日：2016-05-17
申请人： SH MATERIALS CO., LTD.
发明人： Kaoru Hishiki , Ichinori Iidani
IPC分类号： H01L23/52 , H01L23/528 , H01L23/495 , H01L23/00 , H01L23/31 , H01L21/48
CPC分类号： H01L23/5283 , H01L21/4828 , H01L21/4832 , H01L23/3107 , H01L23/49503 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L23/49861 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/97 , H01L2224/29294 , H01L2224/29339 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/85385 , H01L2224/85439 , H01L2224/85444 , H01L2224/85455 , H01L2224/85464 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01028 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/181 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.

8. 发明授权

US10181436B2 Lead frame and method of manufacturing the same 有权
公开(公告)号：US10181436B2
公开(公告)日：2019-01-15
申请号：US15848550
申请日：2017-12-20
申请人： SH MATERIALS CO., LTD.
发明人： Jun Fukuzaki
IPC分类号： H01L23/495 , H01L21/48 , H01L23/00
摘要： A lead frame includes leads including inner leads and outer leads. Each of the leads includes an inner lead and an outer lead. A tie bar extends so as to cross connecting points of the inner leads and the outer leads. The leads and the tie bar include a first surface, a second surface, and side surfaces. A plating layer is provided on the inner leads, the outer leads and the tie bar. A first non-plating region is provided between an edge in the first surface of the inner lead and an edge of the plating layer provided on the first surface of the inner lead. A second non-plating region is provided between an edge of the first surface on the inner lead side of the tie bar and an edge on the inner lead side of the plating layer provided on the first surface of the tie bar.

9. 发明申请

US20160276252A1 LEAD FRAME FOR MOUNTING SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：用于安装半导体元件的引线框架及其制造方法
公开(公告)号：US20160276252A1
公开(公告)日：2016-09-22
申请号：US14777844
申请日：2014-03-18
申请人： SH MATERIALS CO., LTD.
发明人： Ryouichi YOSHIMOTO , Ryohei YAMASHITA
IPC分类号： H01L23/495 , H01L21/48
CPC分类号： H01L23/49548 , H01L21/4828 , H01L23/49503 , H01L23/4952 , H01L23/49541 , H01L23/49582 , H01L2924/0002 , H01L2924/00
摘要： A lead frame for mounting semiconductor element includes a protrusion that is horizontally projects from edges of the upper and lower surfaces of a semiconductor-mounting part or a terminal part of the lead frame and that is provided on a lateral side of at least one of the semiconductor-mounting part or the terminal part of the lead frame, wherein the top end of the protrusion is substantially flat or the profile of the cross section of the top end is arc-shaped, and the top end of the protrusion is thick.
摘要翻译：用于安装半导体元件的引线框架包括从半导体安装部件或引线框架的端子部分的上表面和下表面的边缘水平突出并且设置在引线框架的至少一个的侧面上的突起半导体安装部分或引线框架的端子部分，其中突起的顶端基本上是平坦的，或者顶端的横截面的轮廓是弧形的，并且突起的顶端是厚的。

10. 发明授权

US09054116B2 Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package 有权
标题翻译：用于半导体封装的衬底的制造方法，半导体封装的制造方法，半导体封装的衬底和半导体封装
公开(公告)号：US09054116B2
公开(公告)日：2015-06-09
申请号：US13951612
申请日：2013-07-26
申请人： Yoichiro Hamada , Shigeru Hosomomi
发明人： Yoichiro Hamada , Shigeru Hosomomi
IPC分类号： H01L21/00 , H01L21/56 , H01L21/48 , H01L21/683 , H01L23/498 , H01L23/00 , H01L23/31
CPC分类号： H01L21/56 , H01L21/4846 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/49811 , H01L24/48 , H01L24/49 , H01L24/85 , H01L24/97 , H01L2221/68345 , H01L2224/05554 , H01L2224/48091 , H01L2224/48106 , H01L2224/48247 , H01L2224/49175 , H01L2224/85001 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/15747 , H01L2924/15788 , H01L2924/181 , H01L2924/3025 , H01L2224/85 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.
摘要翻译：半导体封装用基板的制造方法包括：在导电性基板的表面形成抗蚀剂层的抗蚀剂层形成工序; 使用具有包括透射区域，遮光区域和中间透射区域的掩模图案的玻璃掩模曝光抗蚀剂层的曝光步骤，其中中间透射区域的透射率低于透射区域的透射率，并且更高比遮光面积大; 形成抗蚀剂图案的显影步骤，所述抗蚀剂图案包括具有侧面形状的中空部，所述中空部包括当所述中空圆周接近所述基板时在中空圆周上减小的倾斜部分; 以及电镀步骤，在暴露区域上进行平板化以形成具有边缘部分的金属层，所述侧面形状包括随着所述圆周接近所述基板的周边部分减小的倾斜部分。

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