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1. 发明授权

US10510133B2 Asymmetric multi-core heterogeneous parallel processing system 有权
公开(公告)号：US10510133B2
公开(公告)日：2019-12-17
申请号：US15687776
申请日：2017-08-28
申请人： THINK SILICON SA
发明人： Georgios Keramidas , Iakovos Stamoulis , George Sidiropoulos
IPC分类号： G06T1/20 , G06F9/30 , G06F9/38 , G06F9/46 , G06T15/04 , G06T1/60
摘要： A multi-core asymmetric graphics processing unit (GPU) includes a first group and second group of GPU cores. The first group of GPU cores has a first microarchitecture and a first power consumption profile. The first group of GPU cores is configured to execute a subset of instructions of an instruction set architecture (ISA). The second group of GPU cores have a second microarchitecture and a second power consumption profile higher than the first power consumption profile, and are configured to execute the entire ISA. The first group and second group of GPU cores may be further differentiated by a number of pipeline stages, number of registers, branching execution, vectorization units, or combinations thereof. A subset of GPU cores in either group may have a different operation frequency. In some embodiments, an executable instruction may include an indicator to ascertain if execution is performed by the first or second group of GPU cores.

2. 发明授权

US09640149B2 Methods for fixed rate block based compression of image data 有权
公开(公告)号：US09640149B2
公开(公告)日：2017-05-02
申请号：US14804378
申请日：2015-07-21
申请人： THINK SILICON SA
发明人： Georgios Keramidas , Chrysa Kokkala , Iakovos Stamoulis , George Sidiropoulos , Michael Koziotis
IPC分类号： G09F5/00 , G09G5/39 , G06T1/60 , G06T9/00
CPC分类号： G09G5/39 , G06T1/60 , G06T9/00 , G09G5/026 , G09G5/14 , G09G5/363 , G09G5/391 , G09G5/395 , G09G2340/02 , G09G2350/00 , G09G2360/18 , H04N19/119 , H04N19/154 , H04N19/176 , H04N19/196 , H04N19/21 , H04N19/94
摘要： A set of methods, techniques and hardware is described for compressing image data for memory bandwidth and memory storage reduction in graphics processing systems. The disclosed technology can be used for compressing image data sent to the frame buffer and/or image data residing in the frame buffer. The compression process can be based on an adaptive number of base color points and an adaptive number of quantized color points. An adaptive technique for compressing alpha values based on pre-calculated maps or using an estimated alpha value based on thresholds is also disclosed. An implementation of the disclosed methods has, for example, a low hardware overhead, low buffering requirements, and low and predefined compression latency. Also, the disclosed methods allow, for example, random accesses to compressed image data.

3. 发明授权

US09202308B2 Methods of and apparatus for assigning vertex and fragment shading operations to a multi-threaded multi-format blending device 有权
标题翻译：将顶点和片段着色操作分配给多线程多格式混合设备的方法和设备
公开(公告)号：US09202308B2
公开(公告)日：2015-12-01
申请号：US14736553
申请日：2015-06-11
申请人： THINK SILICON LTD
发明人： Georgios Keramidas , Iakovos Stamoulis , George Sidiropoulos , Michael Koziotis
IPC分类号： G09G5/02 , G06T15/50 , G06T1/20 , G09G5/36 , G06F9/38
CPC分类号： G06T15/503 , G06F9/3885 , G06T1/20 , G06T11/00 , G06T11/001 , G06T15/005 , G06T2210/52 , G09G5/363 , G09G2330/021
摘要： An exemplary aspect relates generally to graphics processing systems and more specifically relates to executing vertex and fragment shading operations to a pixel blender device. The technology is at least applicable to graphics processing systems in which vertex and fragment shading operations are executed by dedicated fragment and vertex units or by unified shading units. The graphics processing unit driver is responsible to determine if a shading operation can be assigned to a multi-threaded, multi-format pixel blender. Based on the determination, the fragment shading operations or the vertex shading operations or both are assigned to the pixel blender for execution; the execution of the fragment and/or vertex shading operations by the shader unit(s) is skipped. The determination is based on a code analysis. Forwarding shading operations from the fragment and vertex shaders, i.e., bypassing the shading units, to a programmable, multi-threaded and multi-format pixel blender may save electrical power consumption because a programmable, multi-threaded, and multi-format pixel blender is a less complex circuit compared to a fragment or a vertex or a unified shading unit.
摘要翻译：示例性方面一般涉及图形处理系统，更具体地涉及对像素混合器设备执行顶点和片段着色操作。该技术至少适用于图像处理系统，其中顶点和片段着色操作由专用片段和顶点单元或统一着色单元执行。图形处理单元驱动程序负责确定阴影操作是否可以分配给多线程多格式像素混合器。基于该确定，将片段着色操作或顶点着色操作或两者分配给像素混合器以供执行; 由着色器单元执行片段和/或顶点着色操作被跳过。确定是基于代码分析。将片段和顶点着色器（即，绕过着色单元）转发到可编程的多线程和多格式像素混合器的着色操作可以节省电力消耗，因为可编程的，多线程的和多格式的像素混合器是与片段或顶点或统一着色单元相比较不复杂的电路。

4. 发明授权

US11107180B2 Asymmetric multi-core heterogeneous parallel processing system with content aware and display aware rendering logic 有权
公开(公告)号：US11107180B2
公开(公告)日：2021-08-31
申请号：US16515172
申请日：2019-07-18
申请人： THINK SILICON SA
发明人： Georgios Keramidas , Iakovos Stamoulis , George Sidiropoulos
IPC分类号： G06T1/20 , G06F15/80 , G06F9/50
摘要： An asymmetric multi-core heterogenous parallel processing system includes a first group of graphic processor units (GPUs) and a second group of GPUs. The first and second groups of GPU cores share an instruction set architecture (ISA) such that the first group of GPU cores is capable of executing a portion of the instructions of the ISA, and the second group of GPU cores is capable of executing the entire instruction set of the ISA. An application is capable of utilizing both groups of GPU cores, and is further capable of determining what objects should be rendered on which group of GPU cores.

5. 发明授权

US10748510B2 Framebuffer compression with controllable error rate 有权
公开(公告)号：US10748510B2
公开(公告)日：2020-08-18
申请号：US15873662
申请日：2018-01-17
申请人： THINK SILICON SA
发明人： Georgios Keramidas , Iakovos Stamoulis , Yannis Economou , George Sidiropoulos
IPC分类号： G09G5/395 , G09G5/393 , G06T11/40 , G09G3/20
摘要： The device and method described in this application relate generally to graphics processing systems utilizing the tile based rendering technique and more specifically relate to the processing of the framebuffer data in graphics processing applications. The present invention discloses techniques to reduce the bandwidth needed to access the color data stored in the framebuffer. A method for adaptive lossy delta based compression of color data is disclosed. The error rate, that is the amount of color data lost during the lossy compression process, is controlled by various parameters of the rendered tiles produced by the graphics processing system. The compression process is driven by a dedicated unit which enables informed compression decisions with controllable error rate so as the output color data can be reliably decompressed to produce the original color data with minimal or no errors.

6. 发明授权

US09658851B2 Device and method for approximate memoization 有权
公开(公告)号：US09658851B2
公开(公告)日：2017-05-23
申请号：US14826556
申请日：2015-08-14
申请人： THINK SILICON SA
发明人： Georgios Keramidas , Iakovos Stamoulis , Chrysa Kokkala , George Sidiropoulos
IPC分类号： G06F12/08 , G06F9/302 , G06F9/45 , G06F9/30 , G06F12/0875 , G06F12/0862 , G06F9/38
CPC分类号： G06F9/30058 , G06F7/00 , G06F8/4435 , G06F9/30007 , G06F9/3004 , G06F9/30076 , G06F9/38 , G06F9/3832 , G06F11/00 , G06F12/0862 , G06F12/0875 , G06F2212/452
摘要： An exemplary embodiment relates generally to methods and apparatus of operating a computing device to perform approximate memoizations. Computer code analysis methods, special hardware units, and run-time apparatus that allow limited errors to occur are disclosed. A computer code generation process, part of compiler or interpreter of a computing system, targeting to insert special instructions in the software code of a computer program is also disclosed, wherein the special instructions may embed information to manage the approximation of value memoizations. The presented technology may reduce the electric power consumption of a computing system by reusing the results or part of the results of previous arithmetic or memory operations. Run-time hardware apparatus to manage the elimination of the operations and control the error introduced by approximate value memoizations are also disclosed.

7. 发明授权

US10565677B2 System and method for adaptive z-buffer compression in low power GPUS and improved memory operations with performance tracking 有权
公开(公告)号：US10565677B2
公开(公告)日：2020-02-18
申请号：US15824062
申请日：2017-11-28
申请人： THINK SILICON SA
发明人： Chrysa Kokkala , Georgios Keramidas , Iakovos Stamoulis , George Sidiropoulos
IPC分类号： G06T1/60 , G06F12/0875 , G06T9/00
摘要： Z-buffer compression may be useful for reducing memory usage bandwidth and for performance optimizations. A trackable method of doing the same may be additionally advantageous, as a lossy z-buffer compression scheme may noticeably alter a displayed object. A z-buffer compression unit receives an uncompressed tile, including a matrix of fragments, each representing a pixel and including a z-value. A minimum and maximum z-values of the tile are determined, and a comparison between each z-value of the tile to the minimum/maximum z-value generates a difference value. Basic tile information is then stored, and a compressed tile is stored in the z-buffer memory if the difference value is below a first threshold, such that each fragment is represented by a difference value and an indicator bit, to indicate if the difference is from the minimum z-value or the maximum z-value. The basic tile information includes the minimum z-value, and the maximum z-value.

8. 发明授权

US09899007B2 Adaptive lossy framebuffer compression with controllable error rate 有权
公开(公告)号：US09899007B2
公开(公告)日：2018-02-20
申请号：US13729841
申请日：2012-12-28
申请人： Think Silicon SA
发明人： Iakovos Stamoulis , Georgios Keramidas , George Sidiropoulos
IPC分类号： G09G5/36 , G09G5/395 , G09G5/393 , G06T11/40 , G09G3/20
CPC分类号： G09G5/395 , G06T11/40 , G09G3/2092 , G09G5/393 , G09G2350/00 , G09G2360/12 , G09G2360/122
摘要： The device and method described in this application relate generally to graphics processing systems utilizing the tile based rendering technique and more specifically relate to the processing of the framebuffer data in graphics processing applications. The present invention discloses techniques to reduce the bandwidth needed to access the color data stored in the framebuffer. A method for adaptive lossy delta based compression of color data is disclosed. The error rate, that is the amount of color data lost during the lossy compression process, is controlled by various parameters of the rendered tiles produced by the graphics processing system. The compression process is driven by a dedicated unit which enables informed compression decisions with controllable error rate so as the output color data can be reliably decompressed to produce the original color data with minimal or no errors.

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