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1. 发明授权

US09928361B2 Debug architecture 有权
公开(公告)号：US09928361B2
公开(公告)日：2018-03-27
申请号：US15617953
申请日：2017-06-08
申请人： UltraSoC Technologies Ltd.
发明人： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter McDonald-Maier
IPC分类号： G06F12/00 , G06F21/44 , G06F21/62 , G01R31/317 , G06F12/14 , G06F11/34
CPC分类号： G06F21/44 , G01R31/31705 , G01R31/31719 , G06F11/348 , G06F21/62 , G06F2201/835 , G06F2201/86 , G06F2201/88
摘要： Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.

2. 发明申请

US20130055030A1 Data Processing Apparatus and Related Methods of Debugging Processing Circuitry 审中-公开
标题翻译：数据处理装置及调试处理电路的相关方法
公开(公告)号：US20130055030A1
公开(公告)日：2013-02-28
申请号：US13244023
申请日：2011-09-23
申请人： Andrew Brian Thomas Hopkins , Stephen John Barlow , Constantine Krasic
发明人： Andrew Brian Thomas Hopkins , Stephen John Barlow , Constantine Krasic
IPC分类号： G06F11/30 , G06F11/07
CPC分类号： G06F11/348 , G06F11/3636 , G06F11/3656
摘要： A data processing apparatus, comprising processing circuitry, which in use, generates data and debug circuitry arranged to debug operation of the processing circuitry. The processing circuitry includes bus circuitry arranged to pass data at least one of into and out of the processing apparatus over a communication bus. The debug circuitry comprises monitoring circuitry arranged to monitor the data generated, in use, by the processing circuitry and generate a stream of trace elements. An interface unit is arranged to interface, using the bus circuitry, the trace elements generated by the monitoring circuitry onto the communication bus to be output, in use, from the processing apparatus using the communication bus. The interface unit comprises a controller which is arranged to control operation of the interface unit independently of the operation of the processing circuitry.
摘要翻译：一种数据处理装置，包括处理电路，其在使用中产生被配置为调试处理电路的操作的数据和调试电路。处理电路包括总线电路，其布置成通过通信总线将数据传输到处理设备中的至少一个。调试电路包括监控电路，其被布置为监视在使用中由处理电路产生的数据并产生微量元素流。接口单元布置成使用总线电路将由监视电路产生的微量元件与使用中使用通信总线的处理设备一起输出到通信总线上。接口单元包括控制器，其被配置为独立于处理电路的操作来控制接口单元的操作。

3. 发明申请

US20210103537A1 MESSAGE MONITORING 有权
公开(公告)号：US20210103537A1
公开(公告)日：2021-04-08
申请号：US17064594
申请日：2020-10-06
申请人： UltraSoC Technologies Ltd
发明人： Gajinder Panesar , Iain Robertson , Callum Stewart , Hanan Moller , Melvin Cheah
IPC分类号： G06F13/36
摘要： A supervisory unit configured to supervise interconnect messages passing to or from an interconnect is provided. The supervisory unit is configured to, on receiving an interconnect message: store the interconnect message in a data store; compare the interconnect message to predetermined filter criteria; and select, in dependence on that comparison, one or more actions to be taken with respect to the interconnect message. The one or more actions are selected from the group including: permitting the interconnect message to pass unaltered; blocking the interconnect message from passing and permitting the interconnect message to pass in an altered state; and performing the one or more selected actions with respect to the interconnect message.

4. 发明授权

US10132863B2 Debug architecture 有权
公开(公告)号：US10132863B2
公开(公告)日：2018-11-20
申请号：US14843745
申请日：2015-09-02
申请人： UltraSoC Technologies Ltd.
发明人： Andrew Brian Thomas Hopkins
IPC分类号： G06F1/32 , G06F1/26 , G06F1/00 , G06F9/44 , G01R31/28 , G01R31/317 , G06F1/24 , G06F1/30 , G06F11/36 , G06F11/263 , G06F11/267 , G06F15/78
摘要： Roughly described, a method of powering down a portion of an integrated circuit chip, the portion of the integrated circuit chip comprising a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, the method comprising: prior to power down, extracting from each debug unit configuration information of that debug unit; storing the configuration information of the debug units in a memory on the integrated circuit chip during power down of the portion of the integrated circuit chip; and on power up, restoring the configuration information of each debug unit to that debug unit prior resuming operation of that debug unit and the peripheral circuit connected to that debug unit.

5. 发明授权

US09927486B2 Debug architecture 有权
公开(公告)号：US09927486B2
公开(公告)日：2018-03-27
申请号：US15241805
申请日：2016-08-19
申请人： UltraSoC Technologies Ltd.
发明人： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter Mcdonald-Maier
IPC分类号： G06F12/00 , G11C7/00 , G01R31/28 , G01R31/317 , G06F21/44 , G06F21/62 , G06F21/85 , G06F11/34
CPC分类号： G01R31/2884 , G01R31/31705 , G01R31/31719 , G06F11/27 , G06F11/348 , G06F21/44 , G06F21/62 , G06F21/85 , G06F2201/835 , G06F2201/86 , G06F2201/88
摘要： Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.

6. 发明授权

US09218258B2 Debug architecture 有权
标题翻译：调试架构
公开(公告)号：US09218258B2
公开(公告)日：2015-12-22
申请号：US13938053
申请日：2013-07-09
申请人： UltraSoC Technologies Ltd.
发明人： Andrew Brian Thomas Hopkins
IPC分类号： G06F11/00 , G06F11/22 , G06F11/36 , B01J38/48 , B01J23/04
CPC分类号： G06F11/2205 , B01J23/04 , B01J38/485 , G06F11/3632 , G06F11/3656
摘要： Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit, the respective debug unit configured to generate debug information of that peripheral circuit; and a plurality of separate stores for receiving debug information, storing debug information, and outputting debug information; wherein in response to a single trigger signal, the debug units are configured to stream their generated debug information to the plurality of separate stores; and wherein each of the plurality of separate stores is configured to receive debug information at a higher stream rate than it outputs debug information.
摘要翻译：粗略地描述，集成电路芯片包括多个外围电路，每个外围电路连接到相应的调试单元，相应的调试单元被配置为产生该外围电路的调试信息; 以及多个单独存储器，用于接收调试信息，存储调试信息并输出调试信息; 其中响应于单个触发信号，所述调试单元被配置为将其生成的调试信息流传送到所述多个单独的存储器; 并且其中所述多个单独存储器中的每一个被配置为以比它输出调试信息更高的流速度接收调试信息。

7. 发明授权

US09032109B2 Prioritising event data over configuration data in a single interface in a SoC/debug architecture 有权
标题翻译：在SoC /调试架构中的单个接口中对配置数据进行优先级排序
公开(公告)号：US09032109B2
公开(公告)日：2015-05-12
申请号：US13938046
申请日：2013-07-09
申请人： UltraSoC Technologies Ltd.
发明人： Andrew Brian Thomas Hopkins
IPC分类号： G06F3/00 , G06F11/00 , G06F9/44 , G06F11/36 , G06F15/78
CPC分类号： G06F9/4411 , G06F11/3636 , G06F11/3656 , G06F15/7807
摘要： Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit; a shared hub; and between each respective debug unit and the shared hub, a single physical interface configured to transport both configuration data and event data, wherein the interface is configured such that if an event occurs while the interface is transporting configuration data, the interface interrupts the transport of the configuration data in order to transport the event data.
摘要翻译：粗略地描述，集成电路芯片包括多个外围电路，每个外围电路连接到相应的调试单元; 共享中心并且在每个相应的调试单元和共享集线器之间，被配置为传送配置数据和事件数据的单个物理接口，其中所述接口被配置为使得如果在所述接口正在传输配置数据的情况下发生事件，则所述接口中断配置数据为了传输事件数据。

8. 发明申请

US20170277883A1 DEBUG ARCHITECTURE 有权
公开(公告)号：US20170277883A1
公开(公告)日：2017-09-28
申请号：US15617953
申请日：2017-06-08
申请人： UltraSoC Technologies Ltd.
发明人： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter McDonald-Maier
IPC分类号： G06F21/44 , G01R31/317 , G06F21/62 , G06F11/34
CPC分类号： G06F21/44 , G01R31/31705 , G01R31/31719 , G06F11/348 , G06F21/62 , G06F2201/835 , G06F2201/86 , G06F2201/88
摘要： Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.

9. 发明申请

US20160356841A1 Debug Architecture 有权
标题翻译：调试架构
公开(公告)号：US20160356841A1
公开(公告)日：2016-12-08
申请号：US15241805
申请日：2016-08-19
申请人： UltraSoC Technologies Ltd.
发明人： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter Mcdonald-Maier
IPC分类号： G01R31/28 , G01R31/317
CPC分类号： G01R31/2884 , G01R31/31705 , G01R31/31719 , G06F11/27 , G06F11/348 , G06F21/44 , G06F21/62 , G06F21/85 , G06F2201/835 , G06F2201/86 , G06F2201/88
摘要： Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
摘要翻译：大致描述了一种限制调试控制器访问集成电路芯片上的架构的方法，所述调试架构包括访问控制器，多个外围电路和共享集线器，共享集线器可由访问控制器访问，以及所述多个外围电路，所述方法包括：在所述访问控制器处，认证所述调试控制器; 在访问控制器处，在认证之后向调试控制器分配一组访问权限，授予调试控制器部分访问调试体系结构的一组访问权限; 并且在分配了一组访问权限之后，允许调试控制器访问该组访问权限所允许的调试架构。

10. 发明授权

US10394721B2 Integrated circuit security 有权
公开(公告)号：US10394721B2
公开(公告)日：2019-08-27
申请号：US15365686
申请日：2016-11-30
申请人： UltraSoC Technologies Ltd.
发明人： Gajinder Panesar , Rupert Baines , Iain Robertson
IPC分类号： G06F12/14 , G06F21/56
摘要： An integrated circuit, having a security supervision system, comprising a plurality of functional circuit blocks interconnected to collectively performing data processing tasks, one or more communication adaptors, having: (i) a hardware interconnection to the functional circuit blocks, whereby the communication adaptor senses the state and/or activity of the functional circuit block; (ii) memory storing definitions of state and/or activity of functional circuit block and actions for each definition; and (iii) processing circuitry comparing the state and/or activity of the functional block with each definition, such that when state and/or activity of the functional block corresponding to a stored definition is detected, perform the corresponding action. The memory stores a definition of state and/or activity characteristic of insecure operation of the functional circuit block and a corresponding action to partially disabling the functional circuit block and/or (ii) causing a message to be transmitted to a destination off the integrated circuit.

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