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1. 发明授权

US11545569B2 Method of fabricating a field-effect transistor 有权
公开(公告)号：US11545569B2
公开(公告)日：2023-01-03
申请号：US17038316
申请日：2020-09-30
申请人： X-FAB SEMICONDUCTOR FOUNDRIES GMBH
发明人： Manoj Chandrika Reghunathan , Peter Hofmann
IPC分类号： H01L21/225 , H01L29/78 , H01L29/66 , H01L21/8238 , H01L29/08 , H01L29/06
摘要： A method of fabricating a laterally diffused metal oxide semiconductor transistor including providing a substrate, forming a first well of a first doping polarity type in the substrate, forming a gate on a portion of the first well, the gate including an oxide layer and an at least partially conductive layer on the oxide layer, and forming a mask on at least a portion of the gate and at least a portion of the first well, wherein the mask has a sloping edge. The method further includes forming a second well of a second doping polarity type at least partially in the first well by implanting ions in the first well, the second well extending under a portion of the gate, the second doping polarity type being of opposite type to the first doping polarity type. The method includes forming a first one of a source and drain of the first doping polarity type in or on the second well, thereby defining a channel of the transistor under the gate. The method further includes forming a second one of the source and drain of the first doping polarity type in or on the first well, wherein the implanting includes directing at least a first beam of ions towards the first well at an angle substantially perpendicular to a surface plane of the substrate, and directing at least a second beam of ions towards the first well at an angle substantially offset from a surface normal of the substrate.

2. 发明授权

US10930497B2 Semiconductor substrate and method for producing a semiconductor substrate 有权
公开(公告)号：US10930497B2
公开(公告)日：2021-02-23
申请号：US15877496
申请日：2018-01-23
申请人： X-FAB SEMICONDUCTOR FOUNDRIES GMBH
发明人： Ralf Lerner
IPC分类号： H01L21/00 , H01L21/02 , H01L21/762 , H01L29/06 , H01L29/267
摘要： A method for producing a semiconductor substrate and a semiconductor substrate for use in epitaxial methods of a semiconductor material are described. The semiconductor substrate includes a support slice, an intermediate layer situated on the support slice, and an active layer situated on the intermediate layer. The intermediate layer includes a material which has a reduced viscosity or flows when the semiconductor substrate is used in an epitaxial method in order to enable at least a partial adaptation of a crystal lattice of the active layer to a crystal lattice of the semiconductor material at the transition between the active layer and the semiconductor material.

3. 发明申请

US20210005497A1 Method of manufacturing semiconductor devices to increase yield in microtransfer printing 有权
公开(公告)号：US20210005497A1
公开(公告)日：2021-01-07
申请号：US16921219
申请日：2020-07-06
申请人： X-FAB Semiconductor Foundries GmbH
发明人： Ralf LERNER
IPC分类号： H01L21/683 , H01L25/16 , H01L21/66
摘要： Methods for mounting devices on a non-native substrate by a transfer stamp are disclosed. A method may include providing (102) a first semiconductor wafer (300) comprising mostly functional first devices (304) and a few non-functional first devices (302) in a first grid pattern (x, y); providing (102) a second semiconductor wafer (400) comprising second devices (402) in a second grid pattern (x′, y′); removing (108) the non-functional first devices (302) from the first semiconductor wafer (300) in respective individual first transfer printing steps; transferring (110) a plurality of the functional first devices (304) from the first semiconductor wafer (300) to the associated second devices (402) of the second semiconductor wafer (400) in a second transfer printing step; and transferring (112) individual functional first devices (304) of the first semiconductor wafer (300) to second devices not having first devices printed thereon (408) in respective individual third transfer printing steps.

4. 发明授权

US10825728B2 Electrically conductive via(s) in a semiconductor substrate and associated production method 有权
公开(公告)号：US10825728B2
公开(公告)日：2020-11-03
申请号：US16221930
申请日：2018-12-17
申请人： X-FAB Semiconductor Foundries GmbH
发明人： Roy Knechtel , Sophia Dempwolf , Daniela Guenther , Uwe Schwarz
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/00
摘要： A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure which has been produced or is present on a front side of the substrate; forming at least one contact hole which extends from a surface of a backside of the substrate to a contact surface of the component structure; forming a metal-containing and thus conductive lining in the at least one contact hole creating a hollow electrically conductive structure in the at least one contact hole; and applying a passivation layer over the backside of the substrate, the passivation layer spanning over the hollow electrically conductive structure for forming the at least one electrical via. Also provided is a micro-technical component comprising at least one electrical via.

5. 发明授权

US11355582B2 Trench insulation structure with enlarged electrically conductive side wall 有权
公开(公告)号：US11355582B2
公开(公告)日：2022-06-07
申请号：US16858095
申请日：2020-04-24
申请人： X-FAB Semiconductor Foundries GmbH
发明人： Ralf Lerner
IPC分类号： H01L29/06 , H01L21/762 , H01L23/522
摘要： A semiconductor device may include a first active component region (20) and a second active region (22) extending flat along a first lateral direction (L1) and a second lateral direction (L2) deviating from said first lateral direction. The semiconductor device may include a trench isolation structure (10, 10′) that electrically isolates the first active component region (20) from the second active region (22) along the first lateral direction (L1) and comprises at least one electrically conductive sidewall (14, 14′, 14″); said trench isolation structure (10) having a continuously extending insulating trench isolation base wall (30) and a plurality of spaced apart trench isolation portions (32a, 32b) with electrically conductive sidewall portions (14a, 14b) therebetween. The plurality of trench isolation portions (32a, 32b) and the electrically conductive sidewall portions (14a, 14b) are spaced (a, b) from the base wall (30).

6. 发明申请

US20200020394A1 FLASH MEMORY 审中-公开
公开(公告)号：US20200020394A1
公开(公告)日：2020-01-16
申请号：US16509913
申请日：2019-07-12
申请人： Predrag MICAKOVIC , Holger HABERLA , Andrey HUDYRYEV , Soeren LOHBRANDT
发明人： Predrag MICAKOVIC , Holger HABERLA , Andrey HUDYRYEV , Soeren LOHBRANDT
IPC分类号： G11C11/56 , G11C11/4074 , G11C29/28 , G11C29/34
摘要： A flash memory comprising a first plurality of memory cells, each memory cell of the first plurality of memory cells selectively connected to a first input of a comparator. A second plurality of memory cells selectively connected to a second input of the comparator, wherein a first number of the second plurality of memory cells are in an erased state, wherein a second number of the second plurality of memory cells are in a written state, wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first cell capacitance, and wherein the sum of the first number and the second number is at least three.

7. 发明授权

US11575061B2 Single photon avalanche diode devices 有权
公开(公告)号：US11575061B2
公开(公告)日：2023-02-07
申请号：US16910167
申请日：2020-06-24
申请人： X-FAB Semiconductor Foundries GmbH
发明人： Daniel Gäbler , Hannes Schmidt , Pablo Siles , Matthias Krojer , Alexander Zimmer
IPC分类号： H01L31/107 , H01L27/144 , H01L27/146 , H01L31/02 , H01L31/0216
摘要： A single photon avalanche diode (SPAD) device comprises: a silicon layer; an active region in said silicon layer for detecting incident light; and a blocking structure overlapping said active region for blocking incident light having a wavelength at least in the range of 200 nm to 400 nm, so that light having said wavelength can only be detected by said SPAD device when incident upon a region of said silicon layer outside of said active region.

8. 发明授权

US11081411B2 Semiconductor structure 有权
公开(公告)号：US11081411B2
公开(公告)日：2021-08-03
申请号：US16537945
申请日：2019-08-12
申请人： X-FAB SEMICONDUCTOR FOUNDRIES GMBH
发明人： Matthias Pittner
IPC分类号： H01L21/66 , G01R31/28 , H01L23/544
摘要： A semiconductor structure (100; 200) is provided. The semiconductor structure (100; 200) comprises a substrate (5); a plurality of test structures (101, 102, 201, 202) on the substrate, wherein the plurality of test structures comprise a first set of test structures (101, 102) and a second set of test structures (201, 202); a plurality of test electrodes (10, 20, 30) provided on the substrate, wherein the test electrodes comprise a first set of electrodes (10) operatively connected to the first set of test structures (101, 102), and a second set of electrodes (20) operatively connected to the second set of test structures (201, 202), wherein the first set of electrodes (10) are spaced apart from one another by a predetermined pitch and are configured to be operatively connectable to a probe card (8) having a plurality of probe pins (7) spaced apart from one another by the predetermined pitch to test the first set of test structures, and wherein the second set of electrodes (20) are spaced apart from one another by the predetermined pitch and are configured to be operatively connectable to the probe card (8) to test the second set of test structures; and wherein at least one electrode within the second set of electrodes (20) is disposed between adjacent electrodes within the first set of electrodes (10) along a length of the first set of electrodes (V).

9. 发明申请

US20210149311A1 Geometrically Shaped Components In An Assembly For A Transfer Print And Associated Methods 有权
公开(公告)号：US20210149311A1
公开(公告)日：2021-05-20
申请号：US17101976
申请日：2020-11-23
申请人： X-FAB SEMICONDUCTOR FOUNDRIES GMBH
发明人： Ralf LERNER
IPC分类号： G03F7/20 , H01L23/00 , H01L21/78 , G06F30/392 , H01L21/306 , H01L21/48 , H01L21/768 , H01L23/498
摘要： The invention relates to a geometric design and corresponding methods for components 22, which are produced on a carrier substrate 10 and prepared by detachment in an etching process 30 for a subsequent absorption and a transfer with a stamp for application to a further substrate. The components 22 are designed in such a way that additional active surfaces are provided for the etching process 30 for undercut the components, so that a faster, more reliable and more homogeneous etching profile is achieved.

10. 发明授权

US10186502B1 Integrated circuit having a component provided by transfer print and method for making the integrated circuit 有权
公开(公告)号：US10186502B1
公开(公告)日：2019-01-22
申请号：US15607915
申请日：2017-05-30
申请人： X-FAB SEMICONDUCTOR FOUNDRIES AG
发明人： Ralf Lerner
IPC分类号： H01L23/544 , H01L25/18 , H01L23/538 , H01L23/522 , H01L23/528 , H01L23/00 , H01L25/00 , H01L23/367 , H01L21/683
摘要： A component to be transferred to a receiving substrate is to be coupled both electrically and thermally. This is achieved by an integrated circuit comprising a substrate and a plurality of first components formed in or on the substrate. A plurality of metallization layers are provided. A second component applied by transfer printing is provided which is positioned, at least in part, on a level with and laterally adjacent to at least one of the plurality of metallization layers.

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