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1. 发明申请

US20190095209A1 PROGRAM LOOP CONTROL 审中-公开
公开(公告)号：US20190095209A1
公开(公告)日：2019-03-28
申请号：US16080736
申请日：2017-03-21
申请人： ARM LIMITED
发明人： Alasdair GRANT , Thomas Christopher GROCUTT , Simon John CRASKE
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30065 , G06F9/30036 , G06F9/30145 , G06F9/325 , G06F9/3842
摘要： A data processing system provides a loop-end instruction for use at the end of a program loop body specifying an address of a beginning instruction of said program loop body. Loop control circuitry (1000) serves to control repeated execution of the program loop body upon second and subsequent passes through the program loop body using loop control data provided by the loop-end instruction without requiring the loop-end instruction to be explicitly executed upon each pass.

2. 发明申请

US20180260228A1 SPIN LOOP DELAY INSTRUCTION 审中-公开
公开(公告)号：US20180260228A1
公开(公告)日：2018-09-13
申请号：US15810826
申请日：2017-11-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Fadi Y. Busaba , Christian Jacobi , Anthony Saporito , Eric M. Schwarz , Timothy J. Slegel
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3836 , G06F9/30065 , G06F9/30072 , G06F9/30079 , G06F9/3009 , G06F9/3016 , G06F9/30189 , G06F9/325 , G06F9/3802 , G06F9/381 , G06F9/4806 , G06F9/4843 , G06F9/4881
摘要： A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.

3. 发明申请

US20180181400A1 APPARATUS AND METHODS TO SUPPORT COUNTED LOOP EXITS IN A MULTI-STRAND LOOP PROCESSOR 审中-公开
公开(公告)号：US20180181400A1
公开(公告)日：2018-06-28
申请号：US15391703
申请日：2016-12-27
申请人： Intel Corporation
发明人： Sergey P. Scherbinin , Jayesh Iyer , Alexander Y. Ostanevich , Dmitry Maslennikov , Denis G. Motin , Alexander V. Ermolovich , Andrey Chudnovets , Sergey A. Rozhkov , Boris A. Babayan
IPC分类号： G06F9/32
CPC分类号： G06F9/325 , G06F8/443 , G06F8/4452 , G06F8/452 , G06F9/30065 , G06F9/381 , G06F9/3851 , G06F9/45516
摘要： Embodiments described herein generally relate to the field of multi-strand out-of-order loop processing, and, more specifically, to apparatus and methods to support counted loop exits in a multi-strand loop processor. In one embodiment, a processor includes a loop accelerator comprising a strand documentation buffer and a plurality of strand execution circuits; and a binary translator to receive a plurality of loop instructions, divide the plurality of loop instructions into a plurality of strands, and store a strand documentation for each of the plurality of strands into the strand documentation buffer, each strand documentation indicating at least a number of iterations; wherein the binary translator further causes the loop accelerator to execute the plurality of strands asynchronously and in parallel using the plurality of strand execution circuits, wherein each of the strand execution circuits repeats the strand for the number of iterations indicated in the strand documentation associated with the strand.

4. 发明授权

US09772851B2 Retrieving instructions of a single branch, backwards short loop from a local loop buffer or virtual loop buffer 有权
公开(公告)号：US09772851B2
公开(公告)日：2017-09-26
申请号：US11923709
申请日：2007-10-25
申请人： Ronald Hall , Michael L. Karm , Brian R. Mestan , David Mui
发明人： Ronald Hall , Michael L. Karm , Brian R. Mestan , David Mui
IPC分类号： G06F9/40 , G06F1/32 , G06F9/38 , G06F9/32 , G06F9/30 , G06F12/0875
CPC分类号： G06F9/3802 , G06F1/3234 , G06F9/30189 , G06F9/30196 , G06F9/325 , G06F9/381 , G06F9/3814 , G06F9/3836 , G06F9/3851 , G06F12/0875 , G06F2212/452
摘要： A method, system, and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycles of the single branch, backwards short loop, rather than from the instruction cache.

5. 发明授权

US09715388B2 Instruction and logic to monitor loop trip count and remove loop optimizations 有权
公开(公告)号：US09715388B2
公开(公告)日：2017-07-25
申请号：US13996861
申请日：2012-03-30
申请人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
发明人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/32 , G06F9/30 , G06F9/38 , G06F11/34 , G06F9/45
CPC分类号： G06F9/325 , G06F8/443 , G06F9/30072 , G06F9/3842 , G06F9/3857 , G06F11/3409 , G06F11/348 , G06F2201/88
摘要： Logic and instruction to monitor loop trip count are disclosed. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations may be removed from the loop. The stored loop trip count information may include an identifier identifying the loop, a total loop trip count of the loop, and an exit count of the loop.

6. 发明申请

US20170192787A1 LOOP CODE PROCESSOR OPTIMIZATIONS 审中-公开
公开(公告)号：US20170192787A1
公开(公告)日：2017-07-06
申请号：US14986465
申请日：2015-12-31
申请人： Microsoft Technology Licensing, LLC
发明人： Trishul A. Chilimbi , Olatunji Ruwase , Vivek Seshadri
IPC分类号： G06F9/30 , G06F12/08 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/30192 , G06F9/325 , G06F9/381 , G06F9/3873 , G06F12/0875 , G06F2212/452 , G06N3/08
摘要： Loop code processor optimizations are implemented as a loop optimizer extension to a processor pipeline. The loop optimizer generates optimized code associated with code loops that include at least one zero-optimizable instruction. The loop optimizer may generate multiple versions of optimized code associated with a particular code loop, where each of the multiple version of optimized code has a different associated condition under which the optimized code can be safely executed.

7. 发明授权

US09696996B2 Parallel execution unit that extracts data parallelism at runtime 有权
公开(公告)号：US09696996B2
公开(公告)日：2017-07-04
申请号：US13434903
申请日：2012-03-30
申请人： Alexandre E. Eichenberger , Brian K. Flachs , Charles R. Johns , Mark R. Nutter
发明人： Alexandre E. Eichenberger , Brian K. Flachs , Charles R. Johns , Mark R. Nutter
IPC分类号： G06F9/38 , G06F9/30 , G06F9/32
CPC分类号： G06F9/30076 , G06F9/325 , G06F9/3834 , G06F9/3838
摘要： Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor, Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.

8. 发明授权

US09696995B2 Parallel execution unit that extracts data parallelism at runtime 有权
公开(公告)号：US09696995B2
公开(公告)日：2017-07-04
申请号：US12649805
申请日：2009-12-30
申请人： Alexandre E. Eichenberger , Brian K. Flachs , Charles R. Johns , Mark R. Nutter
发明人： Alexandre E. Eichenberger , Brian K. Flachs , Charles R. Johns , Mark R. Nutter
IPC分类号： G06F9/38 , G06F9/30 , G06F9/32
CPC分类号： G06F9/30076 , G06F9/325 , G06F9/3834 , G06F9/3838
摘要： Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor. Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.

9. 发明授权

US09524011B2 Instruction loop buffer with tiered power savings 有权
标题翻译：指令循环缓冲器，具有分层功率节省
公开(公告)号：US09524011B2
公开(公告)日：2016-12-20
申请号：US14251508
申请日：2014-04-11
申请人： Apple Inc.
发明人： Ronald P. Hall , Michael L. Karm , Ian D. Kountanis , David J. Williamson
IPC分类号： G06F1/26 , G06F1/32 , G06F9/00 , G06F9/30
CPC分类号： G06F1/3234 , G06F9/30058 , G06F9/30065 , G06F9/325 , G06F9/381 , G06F9/3844
摘要： Techniques are disclosed relating to power reduction during execution of instruction loops. Multiple different power saving modes may be used by a processor, such as a first power saving mode after only a few loop iterations (e.g., 2-3) and a second, deeper power saving mode after a greater number of loop iterations. The first power saving mode may include keeping a branch predictor and/or other structures active, but the second power saving mode may include reducing power to the branch predictor and/or other structures. An observation mode and an instruction capture mode may also be used by a processor prior to entering a power saving mode for loop execution. Power saving modes may also be achieved during execution of complex loops having multiple backward branches (e.g., nested loops).
摘要翻译：公开了在执行指令循环期间降低功率的技术。处理器可以使用多种不同的功率节省模式，例如在更多数量的循环迭代之后仅仅几次循环迭代（例如2-3）和第二更深的省电模式之后的第一省电模式。第一省电模式可以包括保持分支预测器和/或其他结构是有效的，但是第二省电模式可以包括降低分支预测器和/或其他结构的功率。在进入用于循环执行的省电模式之前，处理器还可以使用观察模式和指令捕获模式。在执行具有多个后向分支（例如，嵌套循环）的复杂环路时也可以实现节电模式。

10. 发明授权

US09519586B2 Methods and apparatus to reduce cache pollution caused by data prefetching 有权
标题翻译：减少数据预取引起的缓存污染的方法和装置
公开(公告)号：US09519586B2
公开(公告)日：2016-12-13
申请号：US13746000
申请日：2013-01-21
申请人： QUALCOMM Incorporated
发明人： Matthew M. Gilbert
IPC分类号： G06F12/10 , G06F12/08 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38
CPC分类号： G06F12/0862 , G06F9/30065 , G06F9/325 , G06F9/3455 , G06F9/383 , G06F9/3832
摘要： Efficient techniques are described for reducing cache pollution by use of a prefetch logic that recognizes exits from software loops or function returns to cancel any pending prefetch request operations. The prefetch logic includes a loop data address monitor to determine a data access stride based on repeated execution of a memory access instruction in a program loop. Data prefetch logic then speculatively issues prefetch requests according to the data access stride. A stop prefetch circuit is used to cancel pending prefetch requests in response to an identified loop exit. The prefetch logic may also recognize a return from a called function and cancel any pending prefetch request operations associated with the called function. When prefetch requests are canceled, demand requests, such as based on load instructions, are not canceled. This approach to reduce cache pollution uses program flow information to throttle data cache prefetching.
摘要翻译：描述了用于通过使用识别从软件循环退出或函数返回的预取逻辑来减少高速缓存污染以消除任何未决预取请求操作的有效技术。预取逻辑包括循环数据地址监视器，用于基于程序循环中的存储器访问指令的重复执行来确定数据访问步幅。然后，数据预取逻辑根据数据访问步幅推测地发出预取请求。停止预取电路用于响应于所识别的循环出口取消等待的预取请求。预取逻辑还可以识别来自被调用函数的返回并且取消与被调用函数相关联的任何等待预取请求操作。取消预取请求时，不会取消基于加载指令的请求请求。这种减少缓存污染的方法使用程序流信息来限制数据缓存预取。

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