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1. 发明申请

US20180181402A1 PROCESSOR PREFETCH THROTTLING BASED ON SHORT STREAMS 审中-公开
公开(公告)号：US20180181402A1
公开(公告)日：2018-06-28
申请号：US15390588
申请日：2016-12-26
申请人： Intel Corporation
发明人： CHUNHUI ZHANG , SETH H. PUGSLEY , MARK J. DECHENE
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3812 , G06F9/30021 , G06F9/3455 , G06F9/3552 , G06F9/3557 , G06F9/3802 , G06F9/383 , G06F9/3832 , G06F12/0862 , G06F2212/6026
摘要： In an embodiment, a processor comprises a prefetch history array and a prefetch circuit. The prefetch history array comprises a plurality of entries corresponding to prefetch addresses, each entry of the plurality of entries comprising a sublength value associated with a frequency that a stride is repeated. The prefetch circuit is to: for each entry of the plurality of entries, adjust the sublength value based on stride matches for an address of the entry; adjust a short stream counter based on the sublength values of the plurality of entries in the prefetch history array; determine whether the short stream counter has exceeded a throttling threshold; and in response to a determination that the short stream counter has exceeded the throttling threshold, throttle a prefetch level of the prefetch circuit. Other embodiments are described and claimed.

2. 发明授权

US09383998B2 MFENCE and LFENCE micro-architectural implementation method and system 有权
公开(公告)号：US09383998B2
公开(公告)日：2016-07-05
申请号：US13440096
申请日：2012-04-05
申请人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
发明人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

3. 发明申请

US20140281440A1 PRECALCULATING THE DIRECT BRANCH PARTIAL TARGET ADDRESS DURING MISSPREDICTION CORRECTION PROCESS 有权
标题翻译：在错误纠正过程中预先分配直接分配部分目标地址
公开(公告)号：US20140281440A1
公开(公告)日：2014-09-18
申请号：US13842835
申请日：2013-03-15
申请人： QUALCOMM INCORPORATED
发明人： Jiajin Tu , Suresh K. Venkumahanti , Brian R. Mestan
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/324 , G06F9/3806 , G06F9/3812 , G06F9/3846 , G06F9/3861
摘要： An example method of storing a partial target address in an instruction cache includes receiving a branch instruction. The method also includes predicting a direction of the branch instruction as being not taken. The method further includes calculating a destination address based on executing the branch instruction. The method also includes determining a partial target address using the destination address. The method further includes in response to the predicted direction of the branch instruction changing from not taken to taken, replacing an offset in an instruction cache with the partial target address.
摘要翻译：将部分目标地址存储在指令高速缓存中的示例性方法包括接收分支指令。该方法还包括预测不采用分支指令的方向。该方法还包括基于执行分支指令来计算目的地地址。该方法还包括使用目的地址确定部分目标地址。该方法进一步包括响应于从未被采取的分支指令的预测方向改变，替换部分目标地址的指令高速缓存中的偏移。

4. 发明授权

US08635603B2 Handling debugger breakpoints in a shared instruction system 失效
标题翻译：在共享指令系统中处理调试器断点
公开(公告)号：US08635603B2
公开(公告)日：2014-01-21
申请号：US12255138
申请日：2008-10-21
申请人： Thomas Michael Gooding , Richard Michael Shok
发明人： Thomas Michael Gooding , Richard Michael Shok
IPC分类号： G06F9/44 , G06F11/00
CPC分类号： G06F9/3812 , G06F11/3648
摘要： A debugger debugs processes that execute shared instructions so a breakpoint set for one process will not cause a breakpoint to occur in the other processes. A breakpoint is set by recording the original instruction at the desired location and writing a trap instruction to the shared instructions at that location. When a process encounters the breakpoint, the process passes control to the debugger for breakpoint processing if the breakpoint was set at that location for that process. If the trap was not set at that location for that process, the cacheline containing the trap is copied to a small scratchpad memory, and the virtual memory mappings are changed to translate the virtual address of the cacheline to the scratchpad. The original instruction is then written to replace the trap instruction in the scratchpad, so the process can execute the instructions in the scratchpad thereby avoiding the trap instruction.
摘要翻译：调试器调试执行共享指令的进程，因此为一个进程设置的断点不会导致在其他进程中发生断点。通过将原始指令记录在所需位置并将陷阱指令写入该位置的共享指令来设置断点。当进程遇到断点时，如果在该进程的该位置设置了断点，则该进程将控制权转移给调试器进行断点处理。如果该进程的该位置未设置陷阱，则将包含该陷阱的缓存线复制到一个小型暂存器内存中，并更改虚拟内存映射，以将缓存线的虚拟地址转换为暂存器。然后写入原始指令以替换暂存器中的陷阱指令，因此该过程可以执行暂存器中的指令，从而避免陷阱指令。

5. 发明授权

US07966479B1 Concurrent vs. low power branch prediction 有权
标题翻译：并发与低功率分支预测
公开(公告)号：US07966479B1
公开(公告)日：2011-06-21
申请号：US11880859
申请日：2007-07-23
申请人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
发明人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , G06F9/3017 , G06F9/30189 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/1027 , G06F12/1054
摘要： An instruction processing circuit includes a decoder circuit, a basic block builder circuit, a multi-block builder circuit, first and second predictor circuits, and a sequencer circuit, where the sequencer circuit is operable, in a first environment, to cause the first predictor circuit to generate a prediction for a particular conditional branch op concurrently with the second predictor circuit generating a prediction for another particular conditional branch op, where the sequencer circuit is also operable, in a second environment, to cause the first predictor circuit to generate a prediction for the particular conditional branch op sequentially with the second predictor circuit generating a prediction for the another particular conditional branch operation.
摘要翻译：指令处理电路包括解码器电路，基本块构建器电路，多块构建器电路，第一和第二预测器电路和定序器电路，其中定序器电路在第一环境中可操作以使第一预测器电路，用于与第二预测器电路同时产生用于特定条件分支运算的预测，以产生另一特定条件分支op的预测，其中定序器电路在第二环境中也可操作，以使第一预测电路产生预测对于特定条件分支，顺序地与第二预测器电路产生对另一特定条件分支操作的预测。

6. 发明授权

US07949854B1 Trace unit with a trace builder 有权
标题翻译：跟踪单元与跟踪构建器
公开(公告)号：US07949854B1
公开(公告)日：2011-05-24
申请号：US11880861
申请日：2007-07-23
申请人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
发明人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/0875 , G06F12/1027 , G06F12/1054
摘要： An instruction processing unit includes a trace builder circuit operable to (i) receive at least a portion of a first type of sequence of operations and to generate, based thereon, a second type of sequence of operations, where the portion includes at most one control transfer instruction that, when present, ends the portion, (ii) receive sets of at least two sequences of operations and to generate, based thereon, a plurality of third type of sequences of operations, where a sequence of operations of the third type includes one or more interior control transfer instructions and is generated from the sequence of operations of the second type and another sequence of operations of the third type, and (iii) retrieve the sequence of operations of the second type and the another sequence of operations of the third type from a cache circuit.
摘要翻译：指令处理单元包括跟踪构建器电路，其可操作以（i）接收第一类型的操作序列的至少一部分并且基于此产生第二类型的操作序列，其中该部分至多包括一个控制传送指令，当存在时结束部分，（ii）接收至少两个操作序列的集合，并且基于此生成多个第三类型的操作序列，其中第三类型的操作序列包括一个或多个内部控制传送指令，并且从第二类型的操作序列和第三类型的另一操作序列生成，以及（iii）检索第二类型的操作序列和第二类操作的另一操作序列第三种类型从缓存电路。

7. 发明申请

US20100131796A1 System and Method for Detecting and Recovering from Errors in an Instruction Stream of an Electronic Data Processing System 审中-公开
标题翻译：在电子数据处理系统的指令流中检测和恢复错误的系统和方法
公开(公告)号：US20100131796A1
公开(公告)日：2010-05-27
申请号：US12641014
申请日：2009-12-17
申请人： Kenneth L. Engelbrecht , Lawrence R. Fontaine , John S. Kuslak , Conrad S. Shimada
发明人： Kenneth L. Engelbrecht , Lawrence R. Fontaine , John S. Kuslak , Conrad S. Shimada
IPC分类号： G06F11/14 , G06F11/10 , G06F12/08
CPC分类号： G06F11/0793 , G06F9/30145 , G06F9/3802 , G06F9/3812 , G06F9/3824 , G06F9/3836 , G06F9/3865 , G06F9/3867 , G06F9/3873 , G06F11/0721 , G06F11/1064 , G06F12/0802
摘要： A system and method are provided for detecting and recovering from errors in an Instruction Cache RAM and/or Operand Cache RAM of an electronic data processing system. In some cases, errors in the Instruction Cache RAM and/or Operand Cache RAM are detected and recovered from without any required interaction of an operating system of the data processing system. Thus, and in many cases, errors in the Instruction Cache RAM and/or Operand Cache RAM can be handled seamlessly and efficiently, without requiring a specialized operating system routine, or in some cases, a maintenance technician, to help diagnose and/or fix the error.
摘要翻译：提供了一种系统和方法，用于检测和恢复电子数据处理系统的指令高速缓存RAM和/或操作数高速缓存RAM中的错误。在某些情况下，指令高速缓存RAM和/或操作数缓存RAM中的错误从数据处理系统的操作系统的任何必需的交互中被检测和恢复。因此，在许多情况下，指令高速缓存RAM和/或操作数高速缓存RAM中的错误可以无缝和高效地处理，而不需要专门的操作系统程序，或者在某些情况下，维护技术人员帮助诊断和/或修复错误。

8. 发明授权

US07716452B1 Translated memory protection apparatus for an advanced microprocessor 有权
公开(公告)号：US07716452B1
公开(公告)日：2010-05-11
申请号：US10438158
申请日：2003-05-13
申请人： Edmund J. Kelly , Robert F. Cmelik , Malcolm J. Wing
发明人： Edmund J. Kelly , Robert F. Cmelik , Malcolm J. Wing
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F9/3808 , G06F9/3812 , G06F9/45504 , G06F13/4239
摘要： A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

9. 发明授权

US07606975B1 Trace cache for efficient self-modifying code processing 有权
标题翻译：跟踪缓存，用于高效自修改代码处理
公开(公告)号：US07606975B1
公开(公告)日：2009-10-20
申请号：US11535977
申请日：2006-09-27
申请人： Leonard Eric Shar , Kevin Paul Lawton
发明人： Leonard Eric Shar , Kevin Paul Lawton
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F9/30174 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/1027 , G06F12/1054 , Y02D10/13
摘要： A trace cache for efficient self-modifying code processing enables selective invalidation of entries of the trace cache, advantageously retaining some of the entries in the trace cache even during self-modifying code events. Instructions underlying trace cache entries are monitored for modification in groups, enabling advantageously reduced hardware. Associated with trace cache entries are one or more translation ages, determined when the entry is built by sampling current ages of memory blocks underlying the entry. When the entry is accessed and micro-operations therein are processed, each of the translation ages of the accessed entry are compared with the current ages of the memory blocks underlying the accessed entry. If any of the age comparisons fail, then the micro-operations are aborted and the entry is invalidated. When any portion of a memory block is modified, the current age of the modified memory block is incremented.
摘要翻译：用于高效自修改代码处理的跟踪高速缓存使得能够选择性地使跟踪高速缓存的条目无效，即使在自修改代码事件期间也有利地保留跟踪高速缓存中的一些条目。监控底层跟踪缓存条目的指令以进行组中的修改，从而有利于减少硬件。与跟踪缓存条目相关联的是一个或多个翻译年龄，通过对入口下面的内存块的当前年龄进行抽样来确定条目。当访问条目并处理其中的微操作时，将访问条目的每个翻译年龄与被访问条目下面的存储块的当前年龄进行比较。如果任何年龄比较失败，则微操作将中止，并且条目无效。当存储器块的任何部分被修改时，修改的存储器块的当前时间增加。

10. 发明申请

US20090157981A1 COHERENT INSTRUCTION CACHE UTILIZING CACHE-OP EXECUTION RESOURCES 有权
标题翻译：使用缓存执行资源的相关指令高速缓存
公开(公告)号：US20090157981A1
公开(公告)日：2009-06-18
申请号：US12332291
申请日：2008-12-10
申请人： Ryan C. Kinter , Darren M. Jones , Matthias Knoth
发明人： Ryan C. Kinter , Darren M. Jones , Matthias Knoth
IPC分类号： G06F12/08 , G06F9/30
CPC分类号： G06F9/3834 , G06F9/30047 , G06F9/3812 , G06F9/3877 , G06F9/3885 , G06F12/0815
摘要： A multiprocessor system maintains cache coherence among processors in a coherent domain. Within the coherent domain, a first processor can receive a command to perform a cache maintenance operation. The first processor can determine whether the cache maintenance operation is a coherent operation. For coherent operations, the first processor sends a coherent request message for distribution to other processors in the coherent domain and can cancel execution of the cache maintenance operation pending receipt of intervention messages corresponding to the coherent request. The intervention messages can reflect a global ordering of coherence traffic in the multiprocessor system and can include instructions for maintaining a data cache and an instruction cache of the first processor. Cache maintenance operations that are determined to be non-coherent can be executed at the first processor without sending the coherent request.
摘要翻译：多处理器系统保持连贯域中的处理器之间的高速缓存一致性。在相干域内，第一处理器可以接收执行高速缓存维护操作的命令。第一处理器可以确定高速缓存维护操作是否是一致的操作。对于相干操作，第一处理器发送一致的请求消息以分发给相干域中的其他处理器，并且可以在收到对应于相干请求的干预消息之前取消高速缓存维护操作的执行。干预消息可以反映多处理器系统中的一致性业务的全局排序，并且可以包括用于维护第一处理器的数据高速缓存和指令高速缓存的指令。确定为非相干的高速缓存维护操作可以在第一处理器处执行，而不发送相干请求。

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