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1. 发明公开

US20240233816A1 LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM 审中-公开
公开(公告)号：US20240233816A1
公开(公告)日：2024-07-11
申请号：US18613301
申请日：2024-03-22
申请人： Vervain, LLC
发明人： G.R. Mohan Rao
IPC分类号： G11C11/56 , G06F11/10 , G06F12/02 , G11C16/16 , G11C16/34 , G11C29/00 , G11C29/52
CPC分类号： G11C11/5635 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G11C11/5621 , G11C11/5678 , G11C16/16 , G11C16/3495 , G11C29/52 , G11C29/76 , G06F2212/7202 , G11C2211/5641
摘要： A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

2. 发明公开

US20240211395A1 TRIM SETTING DETERMINATION ON A MEMORY DEVICE 审中-公开
公开(公告)号：US20240211395A1
公开(公告)日：2024-06-27
申请号：US18528375
申请日：2023-12-04
申请人： Micron Technology, Inc.
发明人： Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
IPC分类号： G06F12/02 , G06F13/16 , G06F16/18 , G11C7/20 , G11C11/406 , G11C16/20 , G11C16/32 , G11C16/34 , G11C29/02 , G11C29/44
CPC分类号： G06F12/0292 , G06F12/0246 , G06F13/1694 , G06F16/1847 , G11C7/20 , G11C11/40607 , G11C16/20 , G11C16/32 , G11C16/3459 , G11C29/028 , G06F2212/7208 , G06F2212/7209 , G11C2029/4402 , G11C2211/5641
摘要： The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.

3. 发明公开

US20240120000A1 LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM 审中-公开
公开(公告)号：US20240120000A1
公开(公告)日：2024-04-11
申请号：US18390193
申请日：2023-12-20
申请人： Vervain, LLC
发明人： G.R. Mohan Rao
IPC分类号： G11C11/56 , G06F11/10 , G06F12/02 , G11C16/16 , G11C16/34 , G11C29/00 , G11C29/52
CPC分类号： G11C11/5635 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G11C11/5621 , G11C11/5678 , G11C16/16 , G11C16/3495 , G11C29/52 , G11C29/76 , G06F2212/7202 , G11C2211/5641
摘要： A controller for managing at least one MLC non-volatile memory space including at least one MLC non-volatile memory element and at least one SLC non-volatile memory space including at least one SLC non-volatile memory element. The controller is adapted to determine if a range of addresses listed by an entry and mapped to the at least one MLC non-volatile memory element fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC memory element as stored data. In the event of such a failure, the controller remaps said entry to an the at least one SLC non-volatile memory element.

4. 发明授权

US11916569B2 Flash memory apparatus and storage management method for flash memory 有权
公开(公告)号：US11916569B2
公开(公告)日：2024-02-27
申请号：US17676853
申请日：2022-02-22
申请人： Silicon Motion, Inc.
发明人： Tsung-Chieh Yang , Hong-Jung Hsu
IPC分类号： H03M13/00 , H03M13/09 , G06F11/10 , G11C11/56 , G11C16/10 , H03M13/15 , G11C16/26
CPC分类号： H03M13/098 , G06F11/108 , G06F11/1072 , G11C11/5628 , G11C16/10 , H03M13/1515 , H03M13/611 , G11C16/26 , G11C2211/5641
摘要： A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

5. 发明公开

US20240013832A1 LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM 审中-公开
公开(公告)号：US20240013832A1
公开(公告)日：2024-01-11
申请号：US18373071
申请日：2023-09-26
申请人： Vervain, LLC
发明人： G.R. Mohan Rao
IPC分类号： G11C11/56 , G06F12/02 , G11C16/34 , G06F11/10 , G11C29/52 , G11C29/00 , G11C16/16
CPC分类号： G11C11/5635 , G06F12/0246 , G11C16/3495 , G06F11/1068 , G06F11/1072 , G11C11/5621 , G11C11/5678 , G11C29/52 , G11C29/76 , G11C16/16 , G06F2212/7202 , G11C2211/5641
摘要： A method for storing data comprises maintaining an address table for a memory space containing volatile memory and nonvolatile memory space. The nonvolatile memory space includes both multi-level cell (MLC) space and single level cell (SLC) space and the volatile memory includes a random access volatile memory element. An address table maps logical and physical addresses adaptable to the system by the address table. The mapping is performed as necessitated by the system to maximize lifetime maps data in at least one of volatile or nonvolatile memories. Storing received data within a controller memory associated with the at least one controller. Controlling access of the MLC and SLC nonvolatile memory elements and the random access volatile memory element for storage of the received data. Transferring the stored received data from the controller memory to a given one of the MLC nonvolatile memory elements in an associated MLC memory module, operable to store the received data in the given one given one of the MLC nonvolatile memory element as stored data. Retaining the received data in the random access volatile memory as retained data associated with the stored data. Performing a data integrity test on the stored data in the given one of the MLC nonvolatile memory elements in the associated one of the MLC memory modules after at least a Write access operation performed thereon. The performing of the data integrity test further comprising reading the stored data to the controller memory and comparing the stored data in the controller memory in the given one of the MLC nonvolatile memory elements to the retained data that was associated with the stored data in the random access volatile memory by the controller during the Write access operation. Remapping, responsive to a failure of the data integrity test performed on the stored data by the controller, the address space to a different physical range of addresses. Transferring data corresponding to the retained data to those remapped physical address from those physical addresses determined to have failed the data integrity test.

6. 发明授权

US11837277B2 Dual slc/qlc programming and resource releasing 有权
公开(公告)号：US11837277B2
公开(公告)日：2023-12-05
申请号：US17455696
申请日：2021-11-19
申请人： Western Digital Technologies, Inc.
发明人： Karin Inbar , Shay Benisty
IPC分类号： G11C11/40 , G11C11/4093 , G11C11/56 , G06F13/16 , G06F11/07
CPC分类号： G11C11/4093 , G06F11/076 , G06F13/1673 , G11C11/5628 , G11C11/5642 , G11C2211/5641
摘要： The present disclosure generally relates to improved foggy-fine programming. Rather than initially writing to SLC and then later performing a foggy write to QLC with the data read from SLC and then a fine write to QLC with data re-read from SLC, the foggy write to QLC can be performed in parallel to the initial writing to SLC using the same buffer. Once the foggy write to QLC has completed, and the writing to SLC has also completed, the data buffer can be released. The data written in SLC is then be read from SLC and passes through a relocation buffer for the first and only time to then be written using fine programming to QLC. Thus, the data only passes through the relocation buffer one time and the relocation buffer can be freed to usage after only one pass of the data therethrough.

7. 发明授权

US11836078B2 Trim setting determination on a memory device 有权
公开(公告)号：US11836078B2
公开(公告)日：2023-12-05
申请号：US17575998
申请日：2022-01-14
申请人： Micron Technology, Inc.
发明人： Aswin Thiruvengadam , Daniel L Lowrance , Peter Feeley
IPC分类号： G06F12/02 , G11C11/406 , G11C16/20 , G11C16/34 , G06F13/16 , G11C16/32 , G06F16/18 , G11C7/20 , G11C29/02 , G11C29/44
CPC分类号： G06F12/0292 , G06F12/0246 , G06F13/1694 , G06F16/1847 , G11C7/20 , G11C11/40607 , G11C16/20 , G11C16/32 , G11C16/3459 , G11C29/028 , G06F2212/7208 , G06F2212/7209 , G11C2029/4402 , G11C2211/5641
摘要： The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.

8. 发明授权

US11735260B2 Semiconductor memory device 有权
公开(公告)号：US11735260B2
公开(公告)日：2023-08-22
申请号：US16184961
申请日：2018-11-08
申请人： Winbond Electronics Corp.
发明人： Yasuhiro Tomita
IPC分类号： G11C13/04 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/003 , G11C13/004 , G11C13/0023 , G11C13/0033 , G11C13/0035 , G11C2013/0083 , G11C2013/0092 , G11C2211/5641 , G11C2211/5646 , G11C2213/79 , G11C2213/82
摘要： A semiconductor memory device capable of satisfying multiple reliability conditions and multiple performance requirements is provided. A variable resistance memory of the disclosure makes it possible to write data in a memory array by changing a write condition according to the type of a write command from the outside. If the write command is an endurance-related command, an endurance algorithm is selected and data is written in an endurance storage area. If the write command is a retention-related command, a retention algorithm is selected and data is written in a retention storage area.

9. 发明授权

US11721404B2 Operation of mixed mode blocks 有权
公开(公告)号：US11721404B2
公开(公告)日：2023-08-08
申请号：US17484777
申请日：2021-09-24
申请人： Micron Technology, Inc.
发明人： Kishore K. Muchherla , Ashutosh Malshe , Preston A. Thomson , Michael G. Miller , Gary F. Besinga , Scott A. Stoller , Sampath K. Ratnam , Renato C. Padilla , Peter Feeley
IPC分类号： G11C16/30 , G11C16/34 , G11C16/12
CPC分类号： G11C16/349 , G11C16/12 , G11C2211/5641
摘要： Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

10. 发明授权

US11693769B2 Garbage collection adapted to memory device life expectancy 有权
公开(公告)号：US11693769B2
公开(公告)日：2023-07-04
申请号：US17527776
申请日：2021-11-16
申请人： Micron Technology, Inc.
发明人： Qing Liang , Deping He , David Aaron Palmer
IPC分类号： G06F12/00 , G06F12/02 , G11C11/16 , G11C16/10 , G11C16/34 , G11C16/04
CPC分类号： G06F12/0253 , G11C11/1659 , G11C16/10 , G06F12/0246 , G06F2212/7205 , G06F2212/7211 , G11C16/0483 , G11C16/3495 , G11C2211/5641
摘要： Systems and methods for adapting garbage collection (GC) operations in a memory device to an estimated device age are discussed. An exemplary memory device includes a memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the wear-indicated device age relative to the actual device age.

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