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1. 发明公开

US20240126708A1 Seamlessly Integrated Microcontroller Chip 审中-公开
公开(公告)号：US20240126708A1
公开(公告)日：2024-04-18
申请号：US18536264
申请日：2023-12-12
申请人： AyDeeKay LLC dba Indie Semiconductor
发明人： Scott David Kee
IPC分类号： G06F13/26 , G06F3/06 , G06F12/06 , G06F12/0866 , G06F13/14 , G06F13/16 , G06F13/28 , G06F13/364 , G06F13/40 , G06F13/42 , G06F21/76
CPC分类号： G06F13/26 , G06F3/0659 , G06F3/0679 , G06F12/0638 , G06F12/0866 , G06F13/14 , G06F13/1668 , G06F13/1684 , G06F13/28 , G06F13/364 , G06F13/4027 , G06F13/4068 , G06F13/4282 , G06F21/76 , G06F2213/0062 , G06F2213/40 , G06F2221/2103
摘要： Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

2. 发明授权

US11940858B2 Probe filter retention based low power state 有权
公开(公告)号：US11940858B2
公开(公告)日：2024-03-26
申请号：US17973061
申请日：2022-10-25
申请人： Advanced Micro Devices, Inc.
发明人： Benjamin Tsien , Amit P. Apte
IPC分类号： G06F1/3228 , G06F1/3234 , G06F1/3296 , G06F12/0831 , G06F13/26
CPC分类号： G06F1/3228 , G06F1/3275 , G06F1/3296 , G06F12/0833 , G06F13/26 , Y02D10/00
摘要： A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

3. 发明授权

US11741033B2 Dynamically configurable interconnect in a seamlessly integrated microcontroller chip 有权
公开(公告)号：US11741033B2
公开(公告)日：2023-08-29
申请号：US17315272
申请日：2021-05-08
申请人： AyDeeKay LLC
发明人： Scott David Kee
IPC分类号： G06F13/26 , G06F13/40 , G06F3/06 , G06F12/06 , G06F12/0866 , G06F13/16 , G06F13/28 , G06F13/364 , G06F13/42 , G06F13/14 , G06F21/76
CPC分类号： G06F13/26 , G06F3/0659 , G06F3/0679 , G06F12/0638 , G06F12/0866 , G06F13/14 , G06F13/1668 , G06F13/1684 , G06F13/28 , G06F13/364 , G06F13/4027 , G06F13/4068 , G06F13/4282 , G06F21/76 , G06F2213/0062 , G06F2213/40 , G06F2221/2103
摘要： Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

4. 发明公开

US20230185744A1 Seamlessly Integrated Microcontroller Chip 审中-公开
公开(公告)号：US20230185744A1
公开(公告)日：2023-06-15
申请号：US17943183
申请日：2022-09-12
申请人： AyDeeKay LLC dba Indie Semiconductor
发明人： Scott David Kee
IPC分类号： G06F13/26 , G06F13/40 , G06F3/06 , G06F12/06 , G06F12/0866 , G06F13/16 , G06F13/28 , G06F13/364 , G06F13/42 , G06F13/14 , G06F21/76
CPC分类号： G06F13/26 , G06F13/4027 , G06F3/0659 , G06F3/0679 , G06F12/0638 , G06F12/0866 , G06F13/1668 , G06F13/28 , G06F13/364 , G06F13/4068 , G06F13/4282 , G06F13/14 , G06F21/76 , G06F13/1684 , G06F2213/0062 , G06F2213/40 , G06F2221/2103
摘要： Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

5. 发明授权

US11216398B2 USB device and data transfer method thereof 有权
公开(公告)号：US11216398B2
公开(公告)日：2022-01-04
申请号：US16801223
申请日：2020-02-26
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Er-Zih Wong , Zhen-Ting Huang , Shih-Chiang Chu , Sung-Kao Liu , Chia-Yi Chang
IPC分类号： G06F13/26 , G06F13/16
摘要： The invention provides a USB device and a data transfer method thereof. The USB device is coupled to a host and transfers at least one packet to the host. The USB device includes a memory, a USB controller, and a transfer management circuit. The memory stores packets. The USB controller is configured to transfer the packets to the host. The transfer management circuit is coupled between the memory and the USB controller and configured to sequentially read the packets from the memory and sequentially transfer the packets to the USB controller, and to perform the following operations: ending the data transfer when a stored content of the memory does not meet a condition for continuing packet transfer; or ending the data transfer when a last transferred packet meets a preset condition and a next packet that follows the last transferred packet does not meet the preset condition.

6. 发明授权

US11113098B2 Interrupt processing method, master chip, slave chip, and multi-chip system 有权
公开(公告)号：US11113098B2
公开(公告)日：2021-09-07
申请号：US16697111
申请日：2019-11-26
申请人： SHENZHEN GOODIX TECHNOLOGY CO., LTD.
发明人： Zhibing Liang , Yifan Li , Zekai Chen
IPC分类号： G06F9/30 , G06F13/26 , G06F9/48 , G06F9/38
摘要： The present disclosure relates to the field of a multi-chip system, and provides an interrupt processing method, a master chip, a slave chip, and a multi-chip system. An interrupt processing method is applied to a master chip and includes: when an interrupt transport request sent by a slave chip through an interrupt line is detected, obtaining all current interrupt requests (irq_s_1-irq_s_N) of the slave chip, the interrupt request (irq_s_1_-irq_s_N) is generated by a first peripheral (4) of the slave chip; obtaining an interrupt subroutine corresponding to each of the interrupt requests (irq_s_1-irq_s_N), and processing the corresponding interrupt request (irq_s_1-irq_s_N) by using the interrupt subroutine. In the embodiments of the present disclosure, all the interrupt requests (irq_s_1-irq_s_N) of the slave chip are mapped to the master chip, so that the interrupt processing flow of the peripheral on the slave chip is simplified.

7. 发明申请

US20210263867A1 MEMORY PROTOCOL WITH COMMAND PRIORITY 有权
公开(公告)号：US20210263867A1
公开(公告)日：2021-08-26
申请号：US17315871
申请日：2021-05-10
申请人： Micron Technology, Inc.
发明人： Robert M. Walker
IPC分类号： G06F13/18 , G06F13/26 , G06F3/06 , G06F12/02
摘要： The present disclosure includes apparatuses and methods related to a memory protocol with command priority. An example apparatus can execute a command that includes a read identification (RID) number based on a priority assigned to the RID number in a register. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.

8. 发明申请

US20210089481A1 Novel RTOS/OS Architecture for Context Switching Without Disabling Interrupts 有权
公开(公告)号：US20210089481A1
公开(公告)日：2021-03-25
申请号：US16578350
申请日：2019-09-22
申请人： Mazen Arakji
发明人： Mazen Arakji
IPC分类号： G06F13/26 , G06F9/52
摘要： The present invention is a novel RTOS/OS architecture that changes the fundamental way that context switching is performed. In all prior operating system implementations, context switching required disabling of interrupts. This opens the possibility that data can be lost. This novel approach consists of a context switching method in which interrupts are never disabled. Two implementations are presented. In the first implementation, the cost is a negligible amount of memory. In the second, the cost is only a minimal impact on the context switching time. This RTOS/OS architecture requires specialized hardware. Concretely, an advanced interrupt controller that supports nesting and tail chaining of prioritized interrupts is needed (e.g. the Nested Vectored Interrupt Controller (NVIC) found on many ARM processors). The novel RTOS/OS architecture redefines how task synchronization primitives such as semaphores and mutexes are released. Whereas previous architectures directly accessed internal structures, this architecture does so indirectly by saving information in shared buffers or setting flags, and then activating a low priority software interrupt that subsequently interprets this data and performs all context switching logic. The software interrupt must be set as the single lowest priority interrupt in the system.

9. 发明申请

US20200320029A1 System and Method of Rerouting an Inter-Processor Communication Link Based on a Link Utilization Value 审中-公开
公开(公告)号：US20200320029A1
公开(公告)日：2020-10-08
申请号：US16905627
申请日：2020-06-18
申请人： Dell Products L.P.
发明人： Stuart Allen Berke , Wade Andrew Butcher
IPC分类号： G06F13/26 , G06F13/42
摘要： In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communication link interfaces.

10. 发明授权

US10732689B2 Controlling the number of powered vector lanes via a register field 有权
公开(公告)号：US10732689B2
公开(公告)日：2020-08-04
申请号：US15638407
申请日：2017-06-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Timothy David Anderson , Duc Quang Bui
IPC分类号： G06F1/3234 , G06F1/28 , G06F13/26 , G06F9/30 , G06F1/3287 , G06F1/3206 , G06F9/38
摘要： The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

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