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1. 发明授权

US11329185B2 Avalanche diode along with vertical PN junction and method for manufacturing the same field 有权
公开(公告)号：US11329185B2
公开(公告)日：2022-05-10
申请号：US17129422
申请日：2020-12-21
申请人： STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
发明人： Laurence Stark
IPC分类号： H01L31/10 , H01L31/02 , H01L31/107 , H01L31/0352 , H01L31/103 , H01L31/18 , H01L29/72 , G01J1/44
摘要： An embodiment method of manufacturing an avalanche diode includes forming a first trench in a substrate material, filling the first trench with a first material that comprises a dopant, and causing the dopant to diffuse from the first trench to form part of a PN junction. An avalanche diode array can be formed to include a number of the avalanche diodes.

2. 发明授权

US11275045B2 Sensor 有权
公开(公告)号：US11275045B2
公开(公告)日：2022-03-15
申请号：US16675558
申请日：2019-11-06
申请人： MINEBEA MITSUMI Inc.
发明人： Taketomo Nakane
IPC分类号： G01N27/22 , G01N27/04 , H01L29/72 , H01L29/66
摘要： A sensor includes a semiconductor substrate, a detector disposed above the semiconductor substrate and configured to output a signal in accordance with a physical quantity, an electrostatic discharge protection circuit including a metal-oxide-semiconductor transistor, and a dummy pattern formed above the semiconductor substrate and formed of a same material as a material of a gate electrode, the gate electrode being included in the electrostatic discharge protection circuit.

3. 发明授权

US10355113B2 Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics 有权
公开(公告)号：US10355113B2
公开(公告)日：2019-07-16
申请号：US15084112
申请日：2016-03-29
申请人： The Board of Trustees of the University of Illinois
发明人： John A. Rogers , Matthew Meitl , Yugang Sun , Heung Cho Ko , Andrew Carlson , Won Mook Choi , Mark Stoykovich , Hanqing Jiang , Yonggang Huang , Ralph G. Nuzzo , Zhengtao Zhu , Etienne Menard , Dahl-Young Khang
IPC分类号： H05K3/30 , H01L29/72 , H01L21/8258 , H05K1/02 , H01L21/02 , H01L27/12 , H01L29/06 , H01L21/48 , H01L23/538 , H05K3/22 , H05K3/20
摘要： In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

4. 发明授权

US09786773B2 Thin-substrate double-base high-voltage bipolar transistors 有权
公开(公告)号：US09786773B2
公开(公告)日：2017-10-10
申请号：US14992971
申请日：2016-01-11
申请人： Ideal Power Inc.
发明人： William C. Alexander
IPC分类号： H01L29/747 , H01L29/74 , H03K17/60 , H03K17/74 , H01L29/72 , H01L29/732 , H03K17/12 , H03K17/567 , H03K17/66 , H01L29/16
CPC分类号： H01L29/747 , H01L29/1608 , H01L29/72 , H01L29/732 , H01L29/7416 , H03K17/12 , H03K17/567 , H03K17/60 , H03K17/665 , H03K17/74
摘要： B-TRAN bipolar power transistor devices and methods, using a drift region which is much thinner than previously proposed double-base bipolar transistors of comparable voltage. This is implemented in a high-bandgap semiconductor material (preferably silicon carbide). Very high breakdown voltage, and fast turn-off, are achieved with very small on-resistance.

5. 发明授权

US09472645B1 Dual control gate spacer structure for embedded flash memory 有权
标题翻译：用于嵌入式闪存的双控制栅极间隔结构
公开(公告)号：US09472645B1
公开(公告)日：2016-10-18
申请号：US14733011
申请日：2015-06-08
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yuan-Tai Tseng , Chang-Ming Wu , Shih-Chang Liu
IPC分类号： H01L29/72 , H01L29/66 , H01L29/792 , H01L27/115 , H01L29/423 , H01L29/51
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/1157 , H01L27/11582 , H01L29/42344 , H01L29/518 , H01L29/6656 , H01L29/66833 , H01L29/792
摘要： The present disclosure relates to a split gate flash memory cell. In some embodiments, the split gate flash memory cell has a select gate separated from a semiconductor substrate by a gate dielectric layer. A control gate is arranged at one side of the select gate. A charge trapping layer has a vertical portion disposed between the select gate and the control gate, and a lateral portion extending under the control gate. A first control gate spacer is arranged on the lateral portion of the charge trapping layer and extends continuously along an outer sidewall of the control gate. A second control gate spacer is arranged on the lateral portion of the charge trapping layer and extends along an outer sidewall of the first control gate spacer. Bottom surfaces of the first and second control gate spacers are substantially co-planar with a bottom surface of the control gate.
摘要翻译：本公开涉及一个分裂门闪存单元。在一些实施例中，分离栅极闪存单元具有通过栅极介电层与半导体衬底分离的选择栅极。控制门设置在选择门的一侧。电荷捕获层具有设置在选择栅极和控制栅极之间的垂直部分和在控制栅极下方延伸的侧向部分。第一控制栅极间隔物布置在电荷捕获层的侧面部分上并且沿控制栅极的外侧壁连续延伸。第二控制栅极间隔物布置在电荷俘获层的侧面部分上并且沿着第一控制栅极间隔物的外侧壁延伸。第一和第二控制栅极间隔物的底表面与控制栅极的底表面基本上共面。

6. 发明授权

US09306103B2 Back contact photovoltaic module with integrated circuitry 有权
标题翻译：背面接触光伏模块与集成电路
公开(公告)号：US09306103B2
公开(公告)日：2016-04-05
申请号：US13723677
申请日：2012-12-21
申请人： E I DU PONT DE NEMOURS AND COMPANY
发明人： Dilip Natarajan , Thomas D Lantzer , Charles Anthony Smith
IPC分类号： H01L29/72 , H01L31/05 , H01L31/18 , H05K1/03 , H01L31/048 , H01L31/049
CPC分类号： H01L31/0516 , H01L31/048 , H01L31/049 , H01L31/1876 , H05K1/03 , Y02E10/50
摘要： A back-contact solar cell module and a process for making such a solar cell module are provided. The module includes a porous wire mounting layer with a plurality of elongated electrically conductive wires mounted thereon. A polymeric encapsulant layer is provided between a rear surface of solar cells of the module and the porous wire mounting layer and is melted to adhere to the solar cells and penetrate the porous wire mounting layer. Back electrical contacts on the solar cells are electrically connected to the electrically conductive wires through the porous wire mounting layer.
摘要翻译：提供背接触太阳能电池模块和制造这种太阳能电池模块的方法。该模块包括多个导线安装层，其上安装有多个细长的导电线。聚合物密封剂层设置在模块的太阳能电池的后表面和多孔线材安装层之间，并被熔化以粘附到太阳能电池并穿透多孔线材安装层。太阳能电池上的背面电接触通过多孔线安装层电连接到导电线。

7. 发明授权

US09263374B2 Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09263374B2
公开(公告)日：2016-02-16
申请号：US13230128
申请日：2011-09-12
申请人： Masachika Masuda , Koji Tomita , Tadashi Okamoto , Yasunori Tanaka , Hiroshi Ohsawa , Kazuyuki Miyano , Atsushi Kurahashi , Hiromichi Suzuki
发明人： Masachika Masuda , Koji Tomita , Tadashi Okamoto , Yasunori Tanaka , Hiroshi Ohsawa , Kazuyuki Miyano , Atsushi Kurahashi , Hiromichi Suzuki
IPC分类号： H01L29/72 , H01L23/495 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/31 , H01L23/36 , H01L25/10 , H01L23/00
CPC分类号： H01L23/49548 , H01L21/4832 , H01L21/568 , H01L21/6836 , H01L23/3107 , H01L23/3121 , H01L23/3128 , H01L23/36 , H01L23/49503 , H01L23/49517 , H01L23/49541 , H01L23/49582 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L25/105 , H01L2221/68327 , H01L2221/68331 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/48247 , H01L2224/48257 , H01L2224/48639 , H01L2224/48664 , H01L2224/4912 , H01L2224/49171 , H01L2224/49173 , H01L2224/49433 , H01L2224/73265 , H01L2224/83005 , H01L2224/834 , H01L2224/85005 , H01L2224/85439 , H01L2224/85464 , H01L2224/92247 , H01L2225/1023 , H01L2225/1029 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/1301 , H01L2924/14 , H01L2924/15311 , H01L2924/15313 , H01L2924/15331 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/01026
摘要： A semiconductor device includes, a lead frame having a die pad and a plurality of leads each disposed around the die pad, a semiconductor element rested on the die pad of the lead frame, and bonding wires for electrically interconnecting the lead of the lead frame and the semiconductor element. The lead frame, the semiconductor element, and the bonding wires are sealed with a sealing resin section. The sealing resin section includes a central region provided over and around the semiconductor device, and a marginal region provided in the periphery of the central region. Thickness of the central region is greater than that of the marginal region.
摘要翻译：一种半导体器件包括：具有管芯焊盘的引线框架和设置在管芯焊盘周围的多个引线;保持在引线框架的管芯焊盘上的半导体元件和用于将引线框架的引线电连接的接合线和半导体元件。引线框架，半导体元件和接合线用密封树脂部分密封。密封树脂部分包括设置在半导体器件上方和周围的中心区域和设置在中心区域周边的边缘区域。中部地区的厚度大于边缘地区的厚度。

8. 发明授权

US09224837B2 Semiconductor structures with pair(s) of vertical field effect transistors, each pair having a shared source/drain region and methods of forming the structures 有权
公开(公告)号：US09224837B2
公开(公告)日：2015-12-29
申请号：US14711069
申请日：2015-05-13
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L29/72 , H01L29/66 , H01L29/78 , H01L21/308 , H01L21/8234 , H01L29/423
CPC分类号： H01L29/66666 , H01L21/3086 , H01L21/823425 , H01L21/823487 , H01L21/84 , H01L27/1203 , H01L29/42392 , H01L29/66484 , H01L29/7827 , H01L29/7831
摘要： Disclosed are semiconductor structures and methods of forming the structures. The structures each comprise a pair of vertical FETs. Specifically, a U-shaped semiconductor body has a horizontal section and two vertical sections. The horizontal section comprises a shared source/drain region for first and second vertical FETs. Each vertical section comprises a channel region and a source/drain region above the channel region for a corresponding one the vertical FETs. In one semiconductor structure, each vertical section has a gate wrapped around the channel region. In another semiconductor structure, each vertical section has a front gate positioned adjacent to the inner vertical surface at the channel region and a back gate positioned adjacent to the outer vertical surface at the channel region. In any case, a contact, which is electrically isolated from the gates, extends vertically to the shared source/drain region in the horizontal section. Optionally, metal strap(s) electrically connect the pair of vertical FETs to adjacent pair(s).

9. 发明授权

US09214569B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09214569B2
公开(公告)日：2015-12-15
申请号：US14467571
申请日：2014-08-25
申请人： Ki Jeong Kim , Jung Ik Oh , Sung Soo Ahn , Dae Hyun Jang
发明人： Ki Jeong Kim , Jung Ik Oh , Sung Soo Ahn , Dae Hyun Jang
IPC分类号： H01L29/72 , H01L29/788 , H01L27/115 , H01L29/792
CPC分类号： H01L29/7889 , H01L27/11517 , H01L27/11563 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/7926
摘要： According to example embodiments, a memory device includes a substrate, a channel region on the substrate, a plurality of gate electrode layers stacked on each other on the substrate, and a plurality of contact plugs. The gate electrode layers are adjacent to the channel region and extend in one direction to define a pad region. The gate electrode layers include first and second gate electrode layers. The contact plugs are connected to the gate electrode layers in the pad region. At least one of the contact plugs is electrically insulated from the from the first gate electrode layer and electrically connected to the second gate electrode layer by penetrating through the first gate electrode layer.
摘要翻译：根据示例性实施例，存储器件包括衬底，衬底上的沟道区，在衬底上彼此堆叠的多个栅电极层和多个接触插塞。栅极电极层与沟道区域相邻并且在一个方向上延伸以限定衬垫区域。栅极电极层包括第一和第二栅电极层。接触插塞连接到焊盘区域中的栅极电极层。所述接触插塞中的至少一个与所述第一栅极电极层电绝缘，并且通过穿过所述第一栅极电极层而与所述第二栅电极层电连接。

10. 发明授权

US09123540B2 Apparatus for high speed signal processing interface 有权
标题翻译：高速信号处理接口装置
公开(公告)号：US09123540B2
公开(公告)日：2015-09-01
申请号：US14068566
申请日：2013-10-31
申请人： Analog Devices, Inc.
发明人： Javier Alejandro Salcedo , Srivatsan Parthasarathy
IPC分类号： H01L29/72 , H01L27/02
CPC分类号： H01L27/0262 , H01L29/7436
摘要： Signal IO protection devices referenced to a single supply are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power supply network, such as a power low supply network or a power high supply network. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. In other implementations, a protection device includes first and second SCRs for providing protection between the signal node and the power low supply network or between the signal node and the power high supply network, and the SCR structures are integrated in a common circuit layout. The protection devices are suitable for single cell data conversion interface protection to a single supply in sub 3V operation.
摘要翻译：本文提供了参考单电源的信号IO保护装置。在某些实施方式中，保护装置包括第一可控硅整流器（SCR）和第一二极管，用于在信号节点和电源网络之间提供保护，诸如电源低供电网络或电源高供电网络。 SCR和二极管结构集成在公共电路布局中，使得某些阱和有源区域在结构之间共享。在其他实施方式中，保护装置包括第一和第二SCR，用于在信号节点和功率低供电网络之间或在信号节点和电力高供电网络之间提供保护，并且SCR结构集成在公共电路布局中。保护装置适用于单电池数据转换接口保护，在3V以下的单电源供电。

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