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1. 发明授权

US11621360B2 Microstructure enhanced absorption photosensitive devices 有权
公开(公告)号：US11621360B2
公开(公告)日：2023-04-04
申请号：US17707429
申请日：2022-03-29
申请人： W&WSENS DEVICES, INC.
发明人： Shih-Yuan Wang , Shih-Ping Wang
IPC分类号： H01L31/0352 , H01L31/075 , H01L31/105 , H01L31/028 , H01L31/0224 , H01L31/107 , H01L31/02 , H01L31/0236 , G02B6/136 , H01L31/0312 , H01L31/036 , H01L31/077 , H01L31/18 , H01L31/054 , G02B6/122 , H01L23/66 , H01L31/0232 , H01L31/024 , H01L31/0304 , H01L31/0745 , G02B6/12
摘要： Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.

2. 发明申请

US20230054279A1 MICROSTRUCTURE ENHANCED ABSORPTION PHOTOSENSITIVE DEVICES 有权
公开(公告)号：US20230054279A1
公开(公告)日：2023-02-23
申请号：US17974325
申请日：2022-10-26
申请人： W&WSens Devices, Inc.
发明人： Shih-Yuan WANG , Shih-Ping Wang
IPC分类号： H01L31/0236 , H01L31/0352 , H01L31/18 , H01L27/144 , H04B10/69 , H01L31/02 , H01L31/0232 , H01L31/09 , H01L31/103 , H01L31/028 , H01L31/107 , H04B10/25 , H04B10/40 , H04B10/80 , G02B1/00 , G02B6/42 , H01L27/146 , H01L31/077 , H01L31/036 , H01L31/075 , H01L31/105
摘要： Microstructures of micro and/or nano holes on one or more surfaces enhance photodetector optical sensitivity. Arrangements such as a CMOS Image Sensor (CIS) as an imaging LIDAR using a high speed photodetector array wafer of Si, Ge, a Ge alloy on SI and/or Si on Ge on Si, and a wafer of CMOS Logic Processor (CLP) ib Si fi signal amplification, processing and/or transmission can be stacked for electrical interaction. The wafers can be fabricated separately and then stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays can be enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors on the same array and can be Ge or Si pixels. The array can be of high speed photodetectors with data rates of 56 Gigabits per second, Gbps, or more per photodetector.

3. 发明授权

US11569398B2 Power photodiode structures and devices 有权
公开(公告)号：US11569398B2
公开(公告)日：2023-01-31
申请号：US17151109
申请日：2021-01-15
申请人： SLT Technologies, Inc
发明人： Drew W. Cardwell , Mark P. D'Evelyn
IPC分类号： H01L31/0232 , H01L31/0216 , H01L31/0224 , H01L31/0304 , G02B6/42 , H01L31/036 , H01L31/109 , H01L31/18 , H01L31/0352
摘要： According to the present disclosure, techniques related to manufacturing and applications of power photodiode structures and devices based on group-III metal nitride and gallium-based substrates are provided. More specifically, embodiments of the disclosure include techniques for fabricating photodiode devices comprising one or more of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, structures and devices. Such structures or devices can be used for a variety of applications including optoelectronic devices, photodiodes, power-over-fiber receivers, and others.

4. 发明授权

US11527520B2 Micro light emitting diode display device 有权
公开(公告)号：US11527520B2
公开(公告)日：2022-12-13
申请号：US16955700
申请日：2018-09-20
申请人： LG DISPLAY CO., LTD.
发明人： Seong Hwan Ju , Hyeon Ho Son , Jin Yeong Kim , Jung Eun Son , Hanchul Park , Hyunwoo Kim
IPC分类号： H01L31/036 , H01L29/15 , H01L29/04 , H01L27/14 , H01L25/16 , H01L33/44 , H01L33/62 , H01L33/32 , H01L33/36
摘要： The present disclosure relates to a micro light emitting diode (LED) display device including a substrate having a plurality of thin film transistors thereon; a plurality of micro light emitting devices (LEDs) on an upper surface of the substrate, the micro LEDs each having a protecting film provided with a first contact hole to expose a portion of an upper surface of a corresponding micro LED; at least one insulating layer covering the micro LED, the insulating layer provided with a second contact hole to expose a portion of the upper surface of the corresponding micro LED; and a connection electrode in the first contact hole and the second contact hole configured to transfer signals to the micro LED, wherein the first contact hole is larger than the second contact hole.

5. 发明申请

US20220259757A1 SILICON INGOT, SILICON BLOCK, SILICON SUBSTRATE, MANUFACTURING METHOD FOR SILICON INGOT, AND SOLAR CELL 有权
公开(公告)号：US20220259757A1
公开(公告)日：2022-08-18
申请号：US17627412
申请日：2020-07-17
申请人： KYOCERA CORPORATION
发明人： Youhei OGASHIWA
IPC分类号： C30B11/14 , H01L31/068 , H01L31/036 , C30B29/06
摘要： An ingot having a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface and the second surface in a first direction includes a first mono-like crystalline portion, a first intermediate portion including a mono-like crystalline section, a second mono-like crystalline portion, a second intermediate portion including a mono-like crystalline section, and a third mono-like crystalline portion. The first mono-like crystalline portion, the first intermediate portion, and the second mono-like crystalline portion are adjacent to one another in sequence in a second direction perpendicular to the first direction. The first mono-like crystalline portion, the second intermediate portion, and the third mono-like crystalline portion are adjacent to one another in sequence in a third direction perpendicular to the first direction and crossing the second direction. The first mono-like crystalline portion and the second mono-like crystalline portion have a greater width than the first intermediate portion in the second direction. The first mono-like crystalline portion and the third mono-like crystalline portion have a greater width than the second intermediate portion in the third direction. Boundaries between the first mono-like crystalline portion and the first intermediate portion and between the second mono-like crystalline portion and the first intermediate portion, and boundaries between the first mono-like crystalline portion and the second intermediate portion and between the third mono-like crystalline portion and the second intermediate portion each include a coincidence boundary.

6. 发明授权

US11387223B2 Display device comprising plurality of light emitting elements overlapping with contact electrodes 有权
公开(公告)号：US11387223B2
公开(公告)日：2022-07-12
申请号：US17021504
申请日：2020-09-15
申请人： Samsung Display Co., Ltd.
发明人： Min Kyu Woo , Kyung Bae Kim , Jin Yeong Kim , Chong Chui Chai
IPC分类号： H01L31/036 , H01L29/15 , H01L29/04 , H01L27/14 , H01L25/16 , H01L25/075 , H01L33/62
摘要： A display device includes a substrate. A first electrode, a second electrode, and a third electrode are on the substrate, and are sequentially arranged along a first direction. A first light emitting element is located between the first electrode and the second electrode. A second light emitting element is located between the second electrode and the third electrode. A first contact electrode overlaps the first electrode and one end of the first light emitting element, and is in contact with the first electrode and the one end of the first light emitting element. A second contact electrode overlaps and is in contact with the other end of the first light emitting element. A third contact electrode overlaps and is in contact with the second electrode and the other end of the second light emitting element. The second contact electrode extends while detouring the third contact electrode.

7. 发明申请

US20220139972A1 TFT PHOTODETECTOR INTEGRATED ON DISPLAY PANEL 有权
公开(公告)号：US20220139972A1
公开(公告)日：2022-05-05
申请号：US17574743
申请日：2022-01-13
申请人： Hoon KIM
发明人： Hoon KIM
IPC分类号： H01L27/146 , G02F1/13357 , G06F3/042 , H01L27/32 , H01L31/113 , G02F1/1333 , H01L31/036 , G06F3/041 , G06V40/13 , G02F1/133
摘要： A method of fabricating a thin-film transistor (TFT) photodetector includes forming diffusion layers on a glass substrate or a transparent flexible substrate, wherein the diffusion layers include a P-type diffusion layer of P-type polycrystalline or amorphous silicon, for use as an active layer and P+-type diffusion layers of amorphous or polycrystalline silicon at both sides of the P-type diffusion layer, forming an insulating oxide layer on the formed diffusion layers, forming an N-type diffusion layer of polycrystalline or amorphous silicon on the insulating oxide film, forming a gate to be used as a light receiving part by photo-patterning the N-type diffusion layer, etching the generated insulating oxide layer except for only a necessary part in a photoresist (PR) patterning process, removing a remaining area of the P+-type diffusion layer except for areas to be used as a source and a drain by etching, and generating electrodes by depositing a metal in etched parts of the insulating oxide film in the source and the drain.

8. 发明授权

US11316064B2 Photodiode and/or PIN diode structures 有权
公开(公告)号：US11316064B2
公开(公告)日：2022-04-26
申请号：US16887375
申请日：2020-05-29
申请人： GLOBALFOUNDRIES U.S. INC.
发明人： Siva P. Adusumilli , John J. Ellis-Monaghan , Mark D. Levy , Vibhor Jain , Andre Sturm
IPC分类号： H01L31/107 , H01L31/105 , H01L31/036 , H01L31/028 , H01L31/0312
摘要： The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one fin including substrate material, the at least one fin including sidewalls and a top surface; a trench on opposing sides of the at least one fin; a first semiconductor material lining the sidewalls and the top surface of the at least one fin, and a bottom surface of the trench; a photosensitive semiconductor material on the first semiconductor material and at least partially filling the trench; and a third semiconductor material on the photosensitive semiconductor material.

9. 发明申请

US20220093826A1 OPTOELECTRONIC SEMICONDUCTOR DEVICE HAVING DIELECTRIC LAYERS, AND METHOD FOR MANUFACTURING THE SAME 有权
公开(公告)号：US20220093826A1
公开(公告)日：2022-03-24
申请号：US17421394
申请日：2019-12-19
申请人： OSRAM Opto Semiconductors GmbH
发明人： Laura Kreiner , Martin Rudolf Behringer
IPC分类号： H01L33/22 , H01L31/036 , H01L31/18 , H01L33/16 , H01L33/44 , H01L31/0216 , H01L33/00 , G03B21/20 , F21S41/14
摘要： An optoelectronic semiconductor device may include a semiconductor body having a first main surface, a first dielectric layer over the first main surface, and a second dielectric layer on a side of the first dielectric layer facing away from the first main surface. The second dielectric layer is patterned to form an ordered photonic structure. The semiconductor body is suitable for emitting or receiving electromagnetic radiation through the first main surface. The first main surface is roughened, and the first dielectric layer is suitable for leveling a roughening of the first main surface.

10. 发明授权

US11276642B2 Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof 有权
公开(公告)号：US11276642B2
公开(公告)日：2022-03-15
申请号：US16996022
申请日：2020-08-18
申请人： Yangtze Memory Technologies Co., Ltd.
发明人： Jifeng Zhu , Jun Chen , Si Ping Hu , Zhenyu Lu
IPC分类号： H01L29/10 , H01L29/76 , H01L31/036 , H01L31/112 , H01L23/528 , H01L21/02 , H01L21/768 , H01L21/683 , H01L21/3213 , H01L27/11556 , H01L27/11582 , H01L23/522 , H01L21/3105
摘要： Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.

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