专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20230133850A1 Input-Output Buffer Tracking Circuitry 有权
公开(公告)号：US20230133850A1
公开(公告)日：2023-05-04
申请号：US17590584
申请日：2022-02-01
申请人： Arm Limited
发明人： Seshagiri Rao Bogi , Gurupadayya Shidaganti , Akshaykumar V Jabi , Vipul Patel Pursottam
IPC分类号： H03K19/0185 , H03K19/003
摘要： Various implementations described herein are directed to a device having an input-output pad configured to receive and supply an input-output pad voltage. The device may include gate tracking circuitry that receives a first voltage, receives a second voltage different than the first voltage, receives node voltages and provides a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage and the node voltages. The device may include output circuitry that receives the first tracking voltage and the second tracking voltage from the gate tracking circuitry and provides the input-output pad voltage to the input-output pad based on the first tracking voltage and the second tracking voltage.

2. 发明申请

US20230129526A1 SWITCHING CIRCUIT, DC/DC CONVERTER, AND CONTROL CIRCUIT THEREOF 有权
公开(公告)号：US20230129526A1
公开(公告)日：2023-04-27
申请号：US18047730
申请日：2022-10-19
申请人： ROHM Co., LTD.
发明人： Shun FUKUSHIMA
IPC分类号： H02M3/158 , H03K17/687 , H03K19/003
摘要： Disclosed is a switching circuit including an input terminal, a switching terminal, a grounding terminal, a bootstrap terminal, a high-side transistor connected between the input terminal and the switching terminal, a low-side transistor connected between the switching terminal and the grounding terminal, a bootstrap capacitor connected between the switching terminal and the bootstrap terminal, a bootstrap switch connected between a constant voltage line and the bootstrap terminal, and a driver circuit configured to turn on the bootstrap switch in a period of time in which the low-side transistor is on and to turn off the bootstrap switch in a period of time in which the low-side transistor is off. The bootstrap switch includes two P-channel metal oxide semiconductor transistors connected in anti-series with each other between the constant voltage line and the bootstrap terminal.

3. 发明授权

US11632111B1 Redundant control system fault protection using only two controllers 有权
公开(公告)号：US11632111B1
公开(公告)日：2023-04-18
申请号：US17518029
申请日：2021-11-03
申请人： Hamilton Sundstrand Corporation
发明人： John A. Dickey
IPC分类号： H03K19/094 , H03K19/003 , H03K19/20
摘要： A control system is provides that includes a logic gate generating an output state signal, and first and second redundant controllers, wherein the first controller is configured to output a first state signal to a first input of the logic gate, and the second controller is configured to output a second state signal to a second input of the logic gate, and wherein the first controller is configured to receive an impedance isolated feedback signal corresponding to the second state signal from the second controller, and the second controller is configured to receive an impedance isolated feedback signal corresponding to the first state signal from the first controller, so that each controller can determine whether both inputs to the logic gate match one another.

4. 发明授权

US11626876B2 Self-isolating output driver 有权
公开(公告)号：US11626876B2
公开(公告)日：2023-04-11
申请号：US17393844
申请日：2021-08-04
申请人： Rambus Inc.
发明人： Panduka Wijetunga , Dhiraj Kumar
IPC分类号： H03K19/007 , H03K19/003
摘要： Push-pull integrated circuit output drivers may interfere with communication by other entities on a bus when an integrated circuit is powered down. When there is no power and/or when the bonding pad is externally driven above the internal supply voltage, the substrate/body/well of the p-channel field effect transistor (PFET) of the output driver is biased to prevent its drain diode from becoming forward biased thereby preventing interference with communication on the bus. Also, when there is no power, driver is powered down or pull up is disabled, the gate of the driver PFET is driven to a voltage that ensures the driver PFET remains off when the bonding pad is externally driven above the internal supply voltage.

5. 发明授权

US11626875B2 Stress reduction on stacked transistor circuits 有权
公开(公告)号：US11626875B2
公开(公告)日：2023-04-11
申请号：US16262327
申请日：2019-01-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Erkan Bilhan , Francisco A. Cano
IPC分类号： H03K19/003 , H03K19/20
摘要： A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

6. 发明申请

US20230088871A1 HIGH-SPEED VOLTAGE CLAMP FOR UNTERMINATED TRANSMISSION LINES 有权
公开(公告)号：US20230088871A1
公开(公告)日：2023-03-23
申请号：US17479058
申请日：2021-09-20
申请人： International Business Machines Corporation
发明人： Chad Andrew Marquart , Glen A. Wiedemeier , Daniel M. Dreps
IPC分类号： H03K5/08 , H03K19/0944 , H03K19/003 , H04L25/02
摘要： A high-speed voltage clamping circuit includes p-type field effect transistor (PFET) biasing circuit, an n-type field effect transistor (NFET) biasing circuit, and a field effect transistor (FET) clamp circuit. The PFET biasing circuit is configured to generate a PFET biasing voltage. The NFET biasing circuit is configured to generate a NFET biasing voltage. The FET clamp circuit is in signal communication with the PFET biasing circuit and the NFET biasing circuit. The PFET biasing circuit controls operation of the clamping circuit in response to a voltage overshoot event and the NFET biasing circuit controls operation of the clamping circuit in response to a voltage undershoot event.

7. 发明授权

US11575379B2 Switch with hysteresis 有权
公开(公告)号：US11575379B2
公开(公告)日：2023-02-07
申请号：US17648492
申请日：2022-01-20
申请人： Delphi Technologies IP Limited
发明人： Kian Mun Ho
IPC分类号： H03K17/60 , H03K17/693 , H01L27/082 , H02M3/158 , H03K19/003
摘要： Switch circuitry including an input terminal (1), said input terminal connected to the base of a first transistor (Q1) via a first resistor (R3), said first transistor being an NPN Bipolar Gate Transistor (Q1), said circuitry further comprising a second resistor (R5) connected between the base of said first transistor (Q1) and ground, and including an output line or terminal (3) connected to the collector of said first transistor (Q1), and wherein the emitter of said first transistor (Q1) is connected to ground (earth), said circuitry further including a second transistor (Q2), said second transistor being a PNP Bipolar Gate Transistor, wherein the collector of said second transistor (Q2) is connected via a third resistor (R8) to the base of said first transistor (Q1), and the emitter of said second transistor (Q2) is connected to said input terminal (1), and wherein the emitter of said second transistor (Q2) is additionally connected to the base of said second transistor (Q2) via a fourth resistor (R11); and the base of said second transistor (Q2) being additionally connected to the output terminal (3) via a fifth resistor (R10) and a diode (D1).

8. 发明授权

US11563037B2 Semiconductor device, and display device and electronic device having the same 有权
公开(公告)号：US11563037B2
公开(公告)日：2023-01-24
申请号：US17476748
申请日：2021-09-16
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Atsushi Umezaki
IPC分类号： G11C19/00 , H01L27/12 , G02F1/1362 , G09G3/20 , G09G3/325 , G09G3/36 , G11C19/28 , H03K19/003 , H03K3/356 , G09G3/3266 , G09G3/3258
摘要： An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

9. 发明授权

US11558054B1 Active gate driving signal optimization 有权
公开(公告)号：US11558054B1
公开(公告)日：2023-01-17
申请号：US17454860
申请日：2021-11-15
申请人： Kabushiki Kaisha Toshiba
发明人： Xiang Wang
IPC分类号： H03K17/00 , H03K19/003 , H03K17/18 , H03K17/16 , H02M1/08 , H03K17/06
摘要： A method for controlling an electrical switch using a driver waveform, wherein the driver waveform comprises: a first time period, T1, associated with a first current, IG_high; a second time period, T2, associated with a second current, IG_low; wherein: the first current of the driver waveform, IG_high, is larger than the second current of the driver waveform, IG_low; and the first time period, T1, has a first duration and the second time period, T2, has a second duration. The method comprising: determining an optimised first duration by repeatedly modifying the first duration until an overshoot in an output waveform generated by switching the electrical switch using the driver waveform is less than a threshold; determining an optimised second duration based on the optimised first duration; and switching the electrical switch using the optimised first duration and the optimised second duration.

10. 发明申请

US20220416790A1 BUFFER CIRCUIT CAPABLE OF REDUCING NOISE 有权
公开(公告)号：US20220416790A1
公开(公告)日：2022-12-29
申请号：US17514789
申请日：2021-10-29
申请人： SK hynix Inc.
发明人： Jin Ha HWANG , Soon Sung AN , Junseo JANG , Jaehyeong HONG
IPC分类号： H03K19/0185 , H03K19/003
摘要： A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式