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41. 发明授权

US06303439B1 Fabrication method for a two-bit flash memory cell 失效
标题翻译：两位闪存单元的制造方法
公开(公告)号：US06303439B1
公开(公告)日：2001-10-16
申请号：US09449297
申请日：1999-11-24
申请人： Robin Lee , Chih-Hung Lin
发明人： Robin Lee , Chih-Hung Lin
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/7887
摘要： A method for fabricating a two-bit flash memory cell is described in which a substrate with a trench formed therein is provided. A conformal tunnel oxide layer is then formed on the substrate, followed by forming polysilicon spacers on the portion of the tunnel oxide layer which covers the sidewalls of the trench. The polysilicon spacers are separated into a first polysilicon spacer on the right sidewall and a second polysilicon spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the polysilicon spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.
摘要翻译：描述了一种用于制造双位闪存单元的方法，其中提供了形成有沟槽的衬底。然后在衬底上形成保形隧道氧化物层，随后在覆盖沟槽侧壁的隧道氧化物层的部分上形成多晶硅间隔物。多晶硅间隔物被分离成右侧壁上的第一多晶硅间隔物和左侧壁上的第二多晶硅间隔物。此后，在多晶硅间隔物上形成栅极氧化层，随后在衬底的栅极氧化物层上形成多晶硅栅极。随后，在衬底中的多晶硅栅极的两侧上形成源/漏区。

42. 发明授权

US06207504B1 Method of fabricating flash erasable programmable read only memory 失效
标题翻译：制造闪存可擦写可编程只读存储器的方法
公开(公告)号：US06207504B1
公开(公告)日：2001-03-27
申请号：US09223337
申请日：1998-12-30
申请人： Alex Hsieh , Chun-Ming Wu , Chih-Hung Lin
发明人： Alex Hsieh , Chun-Ming Wu , Chih-Hung Lin
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of fabricating flash erasable programmable read only memory. A substrate having an isolation structure is provided. A tunnel oxide layer and a floating gate layer are formed in sequence over substrate and are patterned. An ion implantation is performed and a first doped region is formed in the substrate. An oxidation step is performed to form a first oxide layer over the substrate. A nitride/oxide layer and a control gate layer are formed in sequence over the substrate. The control gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer are patterned until the substrate is exposed. An ion implantation step is performed to form a common source region and a drain region in the substrate. Spacers are formed over the sidewalls of the control gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer. A self-aligned silicide step is performed to form silicide layers over the control gate layer, the common source region, and the drain region.
摘要翻译：一种制造闪存可擦除可编程只读存储器的方法。提供具有隔离结构的基板。在衬底上依次形成隧道氧化物层和浮栅，并进行图案化。进行离子注入并且在衬底中形成第一掺杂区域。执行氧化步骤以在衬底上形成第一氧化物层。在衬底上依次形成氮化物/氧化物层和控制栅极层。对控制栅极层，氮化物/氧化物层，第一氧化物层和浮置栅极层进行图案化，直到基板露出为止。执行离子注入步骤以在衬底中形成公共源极区域和漏极区域。间隔件形成在控制栅极层，氮化物/氧化物层，第一氧化物层和浮动栅极层的侧壁上。执行自对准硅化物步骤以在控制栅极层，公共源极区域和漏极区域上形成硅化物层。

43. 发明授权

US5716874A Method of fabricating EPROM memory by individually forming gate oxide and coupling insulator 失效
标题翻译：通过单独形成栅氧化物和耦合绝缘体来制造EPROM存储器的方法
公开(公告)号：US5716874A
公开(公告)日：1998-02-10
申请号：US603248
申请日：1996-02-20
申请人： Joe Ko , Gary Hong , Chih-Hung Lin
发明人： Joe Ko , Gary Hong , Chih-Hung Lin
IPC分类号： H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825
摘要： A method of fabricating an EPROM memory increases a coupling ratio and reduces lateral diffusion by forming a gate oxide layer and a coupling insulator individually. A substrate is provided with a field oxide layer to isolate a predetermined active area. A gate oxide layer is formed on the substrate. On the field oxide layer and the gate oxide layer, a polysilicon layer is deposited and defined, whereby a portion of this polysilicon layer and gate oxide layer form a gate electrode. Using the gate electrode as a mask, the substrate is implanted with impurities to provide source and drain electrodes. A dielectric layer is formed on polysilicon layer. A contact window (via) is formed in a predetermined area of dielectric layer. An insulator is deposited and defined by etching, on dielectric layer and the contact window. On the insulator and dielectric layer, a metal contact layer is deposited and defined to cover the insulator.
摘要翻译：制造EPROM存储器的方法通过单独形成栅极氧化物层和耦合绝缘体来增加耦合比并减小横向扩散。衬底设置有场氧化物层以隔离预定的有效面积。在衬底上形成栅氧化层。在场氧化物层和栅极氧化物层上沉积并限定多晶硅层，由此该多晶硅层和栅极氧化物层的一部分形成栅电极。使用栅电极作为掩模，衬底被注入杂质以提供源极和漏极。介电层形成在多晶硅层上。在电介质层的预定区域中形成接触窗（通孔）。通过在电介质层和接触窗上进行蚀刻来沉积并限定绝缘体。在绝缘体和电介质层上，沉积和限定金属接触层以覆盖绝缘体。

44. 发明申请

US20210225579A1 Structure of Magnetic Inductive Coil Module 有权
公开(公告)号：US20210225579A1
公开(公告)日：2021-07-22
申请号：US16792273
申请日：2020-02-16
申请人： Chih-Hung Lin , Kun-Chuan Chang
发明人： Chih-Hung Lin , Kun-Chuan Chang
IPC分类号： H01F27/28 , H01F27/24 , H01F27/06
摘要： A coil module includes a first coil set; a second coil set, including a first coil body, a second coil body and an insulative separator disposed between the first coil body and the second coil body, the separator having an adopting hole, the first coil body having an open winding surrounding the adapting hole and fixed on a side of the separator, the second coil body having an open winding surrounding the adapting hole and fixed on another side of the separator; and a coil base sheathing the second coil set with exposing the adopting hole. The first coil set surrounds the adopting hole and is fixed on the coil base to form a coil module.

45. 发明申请

US20210218039A1 BOX-IN-BOX STRUCTURE COMPRISING THERMAL CLAY, USE OF THE SAME AND METHOD TO FORM THE SAME 有权
公开(公告)号：US20210218039A1
公开(公告)日：2021-07-15
申请号：US17015102
申请日：2020-09-09
申请人： Rong-Jie Chen , Chih Hung Lin
发明人： Rong-Jie Chen , Chih Hung Lin
IPC分类号： H01M8/0273 , B29C64/118 , B33Y70/00 , B33Y80/00 , H01M8/0284
摘要： A box-in-box structure includes thermal clay, a plate and a film. The thermal clay includes a polyarysulfone material. The thermal clay is in a form of a first box and the film which has at least one side is in a form of a second box. The second box is attached to the first box in the presence of the plate so that the first box accommodates the second box to form a box-in-box structure.

46. 发明申请

US20210218035A1 FUEL CELL WITH MULTIPLE ELECTRIC CONNECTORS 有权
公开(公告)号：US20210218035A1
公开(公告)日：2021-07-15
申请号：US17148573
申请日：2021-01-14
申请人： Rong-Jie Chen , Chih Hung Lin
发明人： Rong-Jie Chen , Chih Hung Lin
IPC分类号： H01M4/86 , H01M4/90 , H01M8/0247 , H01M8/0221
摘要： A zinc-air fuel cell with multiple electric connectors includes: a case forming a space; multiple gas chambers disposed in the space; two air electrode layers disposed in the space and serving as positive electrodes for discharging; a metal layer disposed in the space and serving as a positive electrode for charging; a zinc material disposed in the space and serving as a negative electrode; multiple separators disposed in the space so that the air electrode layers, the zinc material and the metal layer are separately arranged; an electrolyte disposed in the space, capable of flowing to pass through the separators and in contact with the air electrode layers, the metal layer and the zinc material so that the air electrode layers, the zinc material and the metal layer are respectively electrically connected.

47. 发明授权

US09250295B2 High-voltage battery charging simulation system and operating method thereof 有权
标题翻译：高压电池充电模拟系统及其运行方法
公开(公告)号：US09250295B2
公开(公告)日：2016-02-02
申请号：US13553811
申请日：2012-07-19
申请人： Shean-Kwang Chou , Hung-Hsi Lin , Chih-Hung Lin , Sheng-Hua Chen
发明人： Shean-Kwang Chou , Hung-Hsi Lin , Chih-Hung Lin , Sheng-Hua Chen
IPC分类号： G06G7/54 , G01R31/36
CPC分类号： G01R31/36 , G01R31/3651
摘要： The present invention relates to a high-voltage battery charging simulation system that includes a simulation high-voltage battery pack, a simulation battery management system, a multi-party communication device, and a charging station. The voltage of the simulation high-voltage battery pack can be calculated and updated immediately by the simulation battery management system to simulate the feature of real battery pack, so that it can detect the operation of the multi-party communication device and the charging station.
摘要翻译：本发明涉及一种高压电池充电模拟系统，其包括模拟高电压电池组，模拟电池管理系统，多方通信装置和充电站。仿真高压电池组的电压可以通过模拟电池管理系统立即计算和更新，以模拟实际电池组的特征，从而可以检测多方通信设备和充电站的运行情况。

48. 发明授权

US09015908B2 Liquid-tight slide fastener 有权
标题翻译：液密拉链
公开(公告)号：US09015908B2
公开(公告)日：2015-04-28
申请号：US13512504
申请日：2009-11-30
申请人： Satoshi Matsumoto , Chih Hung Lin , Ke Jyun Wu
发明人： Satoshi Matsumoto , Chih Hung Lin , Ke Jyun Wu
IPC分类号： A44B19/32 , A44B19/08 , B05D1/38 , B05D5/00 , A44B19/02
CPC分类号： A44B19/32 , A44B19/02 , Y10T24/25 , Y10T24/2505 , Y10T24/2514 , Y10T24/2539 , Y10T24/2543
摘要： There is provided a liquid-tight slide fastener capable of sufficiently ensuring waterproof property regardless of where fastener elements are formed and capable of sufficiently ensuring attachment strength of the fastener elements to fastener tapes provided with liquid-tight layers. There is also provided a manufacturing method for the liquid-tight slide fastener. The liquid-tight slide fastener includes a pair of fastener tapes that include a pair of tape members, core sections respectively provided on opposing tape edges of the pair of tape members, and liquid-tight layers formed on one side of the pair of tape members; a pair of fastener element rows; and a slider. The liquid-tight layers are formed with gaps to the core sections in a width direction of the fastener tapes. The fastener elements are attached to the core sections.
摘要翻译：提供了一种能够充分确保防水性能的液密拉链，而不管紧固件元件何时形成，并且能够充分确保拉链件与设置有液密层的拉链带的附接强度。还提供了一种用于液密拉链的制造方法。液密拉链包括一对拉链带，其包括一对带构件，分别设置在一对带构件的相对带边缘上的芯部分，以及形成在一对带构件的一侧上的液密层 ; 一对拉链牙列; 和滑块。液密层在拉链带的宽度方向上与芯部分形成间隙。紧固件元件附接到芯部分。

49. 外观设计

USD722770S1 Tool box 有权
公开(公告)号：USD722770S1
公开(公告)日：2015-02-24
申请号：US29479823
申请日：2014-01-21
申请人： Chih-Hung Lin
设计人： Chih-Hung Lin

50. 发明授权

US08872184B2 Array structure and fabricating method thereof 有权
标题翻译：阵列结构及其制造方法
公开(公告)号：US08872184B2
公开(公告)日：2014-10-28
申请号：US12712209
申请日：2010-02-25
申请人： Yu-Cheng Chen , Chih-Hung Lin , Yi-Hui Li
发明人： Yu-Cheng Chen , Chih-Hung Lin , Yi-Hui Li
IPC分类号： H01L27/14 , H01L29/04 , H01L29/15 , H01L31/036 , H01L27/12 , G02F1/1345 , G02F1/1339 , G02F1/1368 , G02F1/1362
CPC分类号： H01L27/1288 , G02F1/13394 , G02F1/13458 , G02F1/1368 , G02F2001/136231 , H01L27/1214 , H01L27/1248
摘要： An array structure, which includes a TFT, a passivation layer, a pixel electrode, a first connecting layer and a first spacer is provided. The TFT includes a gate, a source and a drain. The passivation layer overlays the TFT. The pixel electrode is located on the passivation layer. The first connecting layer is located on the pixel electrode and electrically connected to the pixel electrode and the drain. The first spacer is located on the first connecting layer.
摘要翻译：提供了包括TFT，钝化层，像素电极，第一连接层和第一间隔物的阵列结构。 TFT包括栅极，源极和漏极。钝化层覆盖TFT。像素电极位于钝化层上。第一连接层位于像素电极上并与像素电极和漏极电连接。第一间隔件位于第一连接层上。

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