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1. 发明授权

US06835619B2 Method of forming a memory transistor comprising a Schottky contact 有权
公开(公告)号：US06835619B2
公开(公告)日：2004-12-28
申请号：US10215898
申请日：2002-08-08
申请人： Kirk D. Prall
发明人： Kirk D. Prall
IPC分类号： H01L21336
CPC分类号： H01L29/0847 , H01L21/28273 , H01L21/28282 , H01L29/66643 , H01L29/7839 , H01L29/7885 , H01L29/792
摘要： A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.

2. 发明授权

US06835610B2 Method of manufacturing semiconductor device having gate electrode with expanded upper portion 失效
标题翻译：制造具有扩大的上部的栅电极的半导体器件的方法
公开(公告)号：US06835610B2
公开(公告)日：2004-12-28
申请号：US10452309
申请日：2003-06-03
申请人： Hirokazu Sayama , Kazunobu Ohta , Hidekazu Oda , Kouhei Sugihara
发明人： Hirokazu Sayama , Kazunobu Ohta , Hidekazu Oda , Kouhei Sugihara
IPC分类号： H01L21336
CPC分类号： H01L21/28052 , H01L21/28044 , H01L21/28114 , H01L21/28518 , H01L21/32155 , H01L21/823835 , H01L21/823842 , H01L29/665
摘要： A method of manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a polysilicon layer on the gate insulating film, implanting ions into the polysilicon layer, patterning the polysilicon layer to form a gate electrode, annealing the gate electrode, and siliciding an upper portion of the gate electrode to form a silicide layer that has a lower portion facing the gate electrode and an upper portion opposite to the lower portion, the upper portion of the silicide layer being wider than the lower portion. A total dose of ions implanted during the step of implanting is 6×1015/cm2 or larger.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成栅极绝缘膜，在栅极绝缘膜上形成多晶硅层，将离子注入到多晶硅层中，构图多晶硅层以形成栅电极，退火栅电极，并且将所述栅电极的上部硅化，以形成具有面向所述栅电极的下部和与所述下部相对的上部的硅化物层，所述硅化物层的上部比所述下部宽。在植入步骤期间植入的离子的总剂量为6×10 15 / cm 2以上。

3. 发明授权

US06830969B2 Method for manufacturing semiconductor device and the device thereof 失效
标题翻译：半导体装置的制造方法及其装置
公开(公告)号：US06830969B2
公开(公告)日：2004-12-14
申请号：US10321631
申请日：2002-12-18
申请人： Won Sic Woo
发明人： Won Sic Woo
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： The present invention relates to a method of manufacturing a semiconductor device. The method comprises the steps of forming a plurality of lower bit lines arranged in a first direction on a semiconductor substrate by performing ion implantation using a mask defining the lower bit lines, forming a lower field oxide film within a region in which the lower bit lines are formed to define an active region and a device isolation region, forming a first insulating film for accumulating charges on the active region, forming a plurality of word lines arranged in parallel in a second direction orthogonal to the first direction of the lower bit lines, depositing an oxide film on the entire structure of the semiconductor substrate including the lower bit lines and the word lines, flattening the oxide film and then removing the oxide film on the word lines, forming a second insulating film for accumulating charges corresponding to the first insulating film for accumulating charges on the word lines and then forming an upper field oxide film corresponding to the lower field oxide film on the word lines, depositing polysilicon on the entire structure of the semiconductor substrate, performing ion implantation using a mask defining upper bit lines for polysilicon to form the upper bit lines, and then performing ion implantation using a mask defining an upper substrate to form the upper substrate, and removing given portions of the upper bit lines formed on the upper field oxide film to separate the upper bit lines.
摘要翻译：本发明涉及半导体器件的制造方法。该方法包括以下步骤：通过使用限定下位线的掩模进行离子注入，在半导体衬底上形成沿第一方向布置的多个下位线，在下位线的区域内形成下场氧化膜形成有源区和器件隔离区，形成用于在有源区积累电荷的第一绝缘膜，形成沿与下位线的第一方向正交的第二方向平行布置的多个字线，在包括下位线和字线的半导体衬底的整个结构上沉积氧化膜，使氧化膜平坦化，然后去除字线上的氧化膜，形成用于累积与第一绝缘体相对应的电荷的第二绝缘膜用于在字线上累积电荷，然后形成对应于下场氧化物的上场氧化膜在半导体衬底的整个结构上沉积多晶硅，使用定义用于多晶硅的上位线的掩膜进行离子注入以形成高位线，然后使用限定上基板的掩模进行离子注入以形成并且去除形成在上场氧化膜上的上位线的给定部分以分离高位线。

4. 发明授权

US06828202B1 Semiconductor region self-aligned with ion implant shadowing 失效
标题翻译：半导体区域与离子植入物阴影自对准
公开(公告)号：US06828202B1
公开(公告)日：2004-12-07
申请号：US10400943
申请日：2003-03-27
申请人： Andrew Horch
发明人： Andrew Horch
IPC分类号： H01L21336
CPC分类号： H01L29/66242 , H01L27/11 , H01L29/7436 , H01L29/7455
摘要： A semiconductor device includes doped regions of a substrate spaced at selected distances from features at an upper surface of the substrate. According to an example embodiment of the present invention, the doped regions are implanted and spaced apart from the features with the height of the features and the angle of an implant used for implanting the doped regions setting the space between the doped regions and the features. In one implementation, the height of the features is varied (e.g., with the features being defined using different steps, such as photolithography) to set the spacing of different doped regions. In another implementation, the angle of the implant is varied to set the spacing for different doped regions. In still another implementation, both the height of the features and angle of the implant are varied to set the spacing for different doped regions. With these approaches, alignment and spacing of doped features is achieved using a process that is predictable and controllable, which can reduce variations typically present in connection with other commonly-used alignment techniques, such as photolithography.
摘要翻译：半导体器件包括在衬底的上表面上与特征间隔开选定距离的衬底的掺杂区域。根据本发明的示例实施例，掺杂区域被注入并且与特征的高度相隔离，并且用于植入掺杂区域的植入物的角度设置掺杂区域和特征之间的空间。在一个实施方式中，特征的高度是变化的（例如，使用不同步骤来定义特征，例如光刻）以设定不同掺杂区域的间隔。在另一实施方案中，改变注入的角度以设定不同掺杂区域的间隔。在又一实施方式中，改变注入的特征的高度和角度，以设定不同掺杂区域的间隔。利用这些方法，使用可预测和可控的过程来实现掺杂特征的对准和间隔，这可以减少通常与其它通常使用的对准技术（例如光刻）结合的变化。

5. 发明授权

US06828198B2 System-on-chip (SOC) solutions with multiple devices by multiple poly gate trimming process 失效
公开(公告)号：US06828198B2
公开(公告)日：2004-12-07
申请号：US10392120
申请日：2003-03-19
申请人： Hung-Der Su , Shien-Yang Wu , Yung-Shun Chen , Tung-Heng Shie , Yuan-Hung Chiu
发明人： Hung-Der Su , Shien-Yang Wu , Yung-Shun Chen , Tung-Heng Shie , Yuan-Hung Chiu
IPC分类号： H01L21336
CPC分类号： H01L21/823456 , H01L21/28123 , H01L21/32139
摘要： A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.

6. 发明授权

US06825087B1 Hydrogen anneal for creating an enhanced trench for trench MOSFETS 有权
标题翻译：用于产生用于沟槽MOSFET的增强沟槽的氢退火
公开(公告)号：US06825087B1
公开(公告)日：2004-11-30
申请号：US09448884
申请日：1999-11-24
申请人： Joelle Sharp , Gordon K. Madson
发明人： Joelle Sharp , Gordon K. Madson
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L21/324 , H01L21/3247
摘要： A method of forming a trench in a substrate or in an epitaxial layer, previously grown over the semiconductor substrate, wherein an anneal step, using hydrogen gas results in rounded corners without the need for a rounding etch or any other processing steps to round the corners.
摘要翻译：在半导体衬底上预先生长的衬底或外延层中形成沟槽的方法，其中使用氢气的退火步骤产生圆角，而不需要舍入蚀刻或任何其他处理步骤来绕圆角。

7. 发明授权

US06825086B2 Strained-silicon channel CMOS with sacrificial shallow trench isolation oxide liner 失效
标题翻译：应变硅沟道CMOS与牺牲浅沟槽隔离氧化物衬垫
公开(公告)号：US06825086B2
公开(公告)日：2004-11-30
申请号：US10345728
申请日：2003-01-17
申请人： Jong-Jan Lee , Sheng Teng Hsu
发明人： Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21336
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823807
摘要： A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method comprises: forming a Si substrate; forming a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer; forming a strained-Si layer overlying the relaxed-SiGe layer; forming a silicon oxide layer overlying the strained-Si layer; forming a silicon nitride layer overlying the silicon oxide layer; etching the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface; forming a sacrificial oxide liner on the STI trench surface; in response to forming the sacrificial oxide liner, rounding and reducing stress at the STI trench corners; removing the sacrificial oxide liner; and, filling the STI trench with silicon oxide.
摘要翻译：已经提供了应变硅（Si）沟道CMOS器件浅沟槽隔离（STI）氧化物区域及其形成方法。该方法包括：形成Si衬底; 形成覆盖在Si衬底上的弛豫SiGe层或者具有掩埋氧化物（BOX）层的绝缘体上硅锗（SGOI）衬底; 形成覆盖弛豫SiGe层的应变Si层; 形成覆盖在应变Si层上的氧化硅层; 形成覆盖所述氧化硅层的氮化硅层; 蚀刻氮化硅层，氧化硅层，应变Si层和弛豫SiGe层，形成具有沟槽角和沟槽表面的STI沟槽; 在STI沟槽表面上形成牺牲氧化物衬垫; 响应于形成牺牲氧化物衬垫，在STI沟槽角处减少应力; 去除牺牲氧化物衬垫; 并用氧化硅填充STI沟槽。

8. 发明授权

US06821855B2 Reverse metal process for creating a metal silicide transistor gate structure 有权
标题翻译：用于产生金属硅化物晶体管栅极结构的反向金属工艺
公开(公告)号：US06821855B2
公开(公告)日：2004-11-23
申请号：US10230203
申请日：2002-08-29
申请人： Werner Juengling , Richard H. Lane
发明人： Werner Juengling , Richard H. Lane
IPC分类号： H01L21336
CPC分类号： H01L29/66537 , H01L21/26586 , H01L21/28052 , H01L21/28061 , H01L29/4941 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer, a conducting layer, and a first insulating layer. Sidewall spacers are formed adjacent to the sides of the gate stack structure and a third insulating layer is formed over the gate stack and substrate. The third insulating layer and first insulating layer are removed to expose the conducting layer and, at least one unetched metal-containing layer is formed over and in contact with the conducting layer. The gate stack structure then undergoes a siliciding process with different variations to finally form a silicide gate.
摘要翻译：本发明教导了一种形成具有硅化物栅的MOSFET晶体管的方法，其在形成栅极堆叠结构时不会产生通过蚀刻含金属层产生的问题。在包括栅极氧化物层，导电层和第一绝缘层的半导体衬底上形成栅堆叠。侧壁间隔件形成在栅堆叠结构的侧面附近，并且第三绝缘层形成在栅堆叠和衬底上。去除第三绝缘层和第一绝缘层以暴露导电层，并且至少一个未蚀刻的含金属层形成在导电层上并与导电层接触。然后，栅极堆叠结构经历不同变化的硅化处理，最终形成硅化物栅极。

9. 发明授权

US06818516B1 Selective high k dielectrics removal 失效
标题翻译：选择性高k电介质去除
公开(公告)号：US06818516B1
公开(公告)日：2004-11-16
申请号：US10629496
申请日：2003-07-29
申请人： Wai Lo , Hong Lin , Shiqun Gu , James R. B. Elmer
发明人： Wai Lo , Hong Lin , Shiqun Gu , James R. B. Elmer
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/31111
摘要： A method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode layer is the patterned. LDD regions are formed using an ion implantation process, thereby creating damaged portions of the high k layer. A first portion of the damaged portions of the high k layer are removed, thereby defining a gate structure, and leaving remaining portions of the damaged portions of the high k layer. Sidewall spacers are formed adjacent the gate structure. Source/drain regions are formed using an ion implantation process, thereby further damaging the remaining portions of the damaged portions of the high k layer. The remaining portions of the damaged portions of the high k layer are then removed.
摘要翻译：在基板上的集成电路中形成栅极结构的方法。在基板上形成高k层，在高k层上形成栅电极层。栅极电极层是图案化的。使用离子注入工艺形成LDD区域，从而产生高k层的损坏部分。去除高k层的损坏部分的第一部分，从而限定栅极结构，并留下高k层的损坏部分的剩余部分。侧壁间隔件形成在栅极结构附近。使用离子注入工艺形成源极/漏极区，从而进一步损坏高k层的损伤部分的剩余部分。然后去除高k层的损坏部分的剩余部分。

10. 发明授权

US06818515B1 Method for fabricating semiconductor device with loop line pattern structure 有权
标题翻译：制造具有环线图形结构的半导体器件的方法
公开(公告)号：US06818515B1
公开(公告)日：2004-11-16
申请号：US10600466
申请日：2003-06-23
申请人： Brian S. Lee , Chih-Yu Lee
发明人： Brian S. Lee , Chih-Yu Lee
IPC分类号： H01L21336
CPC分类号： H01L21/32139 , G03F1/30 , H01L27/10861 , H01L27/10891
摘要： An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip.
摘要翻译：具有暗环的交替相移掩模，用交替相移掩模制造的存储器阵列，以及制造存储器的方法。掩模中的暗环总是将具有180°相位差的第一区域与具有0°相位差的第二区域分开，以限定DRAM芯片中的有源区或栅极线。

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