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51. 发明申请

WO2008153164A2 MIH PRE-AUTHENTICATION 审中-公开
标题翻译： MIH预认证
公开(公告)号：WO2008153164A2
公开(公告)日：2008-12-18
申请号：PCT/JP2008060922
申请日：2008-06-09
申请人： TOSHIBA KK , TELCORDIA TECH INC , OBA YOSHIHIRO , DAS SUBIR
发明人： OBA YOSHIHIRO , DAS SUBIR
IPC分类号： H04L9/32 , H04W12/04 , H04W36/00
CPC分类号： H04W12/06 , H04L63/0823 , H04W36/0011 , H04W36/005 , H04W60/005
摘要： A system and method for performing MIH pre-authentication, which includes providing support for both direct and/or indirect pre-authentication and providing support for both network-initiated and mobile-initiated pre-authentication.
摘要翻译：一种用于执行MIH预认证的系统和方法，其包括为直接和/或间接预认证提供支持，并且为网络启动和移动发起的预认证提供支持。

52. 发明申请

WO2008099723B1 SEMICONDUCTOR MEMORY WITH REED- SOLOMON DECODER 审中-公开
标题翻译：半导体存储器与REED- SOLOMON解码器
公开(公告)号：WO2008099723B1
公开(公告)日：2008-10-23
申请号：PCT/JP2008051903
申请日：2008-01-30
申请人： TOSHIBA KK , TODA HARUKI
发明人： TODA HARUKI
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/1575 , G06F11/1068 , H03M13/1515
摘要： A semiconductor memory device such as a flash memory with a memory cell array and a double-error correcting Reed-Solomon decoder, comprising: means for transforming the error location polynomial through variable transformation in order to obtain a unique coefficient depending on the syndromes; a lookup table for determining the error locations from the unique coefficient; and means for determining said unique coefficient from the syndromes through computation in a Residue Number System in order to achieve parallel processing and to reduce the quantity of computations, for example using residues through 15 and 17 when processing in GF (256)
摘要翻译：一种半导体存储器件，例如具有存储单元阵列的闪存和双纠错里德 - 索罗姆解码器的半导体存储器件，包括：用于通过可变变换变换误差位置多项式的装置，以便根据校正子获得独特的系数; 用于从所述唯一系数确定所述错误位置的查找表; 以及用于通过残差编号系统中的计算来确定来自综合征的所述唯一系数的装置，以便实现并行处理并减少计算量，例如当在GF（256）中处理时使用通过15和17的残差，

53. 发明申请

WO2008103488A2 MEDIA INDEPENDENT PRE-AUTHENTICATION SUPPORTING FAST HANDOFF IN PROXY MIPV6 ENVIRONMENT 审中-公开
标题翻译：媒体独立的预认证支持快速移植代码MIPV6环境
公开(公告)号：WO2008103488A2
公开(公告)日：2008-08-28
申请号：PCT/US2008002436
申请日：2008-02-25
申请人： TOSHIBA KK , TELCORDIA TECH INC , TANIUCHI KENICHI , DUTTA ASHUTOSH , FAJARDO VICTOR , OBA YOSHIHIRO
发明人： TANIUCHI KENICHI , DUTTA ASHUTOSH , FAJARDO VICTOR , OBA YOSHIHIRO
IPC分类号： H04W12/06 , H04W36/00 , H04W80/04 , H04W88/18
CPC分类号： H04W36/0011 , H04L63/0272 , H04L63/0281 , H04W12/06 , H04W36/0033 , H04W80/04 , H04W88/182
摘要： This document describes a proactive mechanism to provide fast- handover involving PMIPv6. In particular, it describes how one can achieve fast handoff for PIMPv6 using Media- independent Pre- Authentication (MPA) technique. It discusses the need for a fast- handoff for PIMPv6 environment. It then describes how MPA techniques could be used during different steps involving both intra-domain and inter-domain handoff for PIMPv6. MPA-based fast-handover takes advantage of the pre-authentication mechanism so that the mobile can perform the access authentication while in the previous local mobility (PMA) domain and thus would be able to complete many of the handoff related operations while still in the previous network.
摘要翻译：本文档描述了一种主动机制，提供涉及PMIPv6的快速切换。特别地，它描述了如何使用媒体独立的预认证（MPA）技术实现PIMPv6的快速切换。它讨论了PIMPv6环境快速切换的需要。然后介绍如何在涉及PIMPv6的域内和域间切换的不同步骤中使用MPA技术。基于MPA的快速切换利用预认证机制，使得移动台可以在先前的本地移动性（PMA）域中执行接入认证，并且因此能够完成许多与切换相关的操作，同时仍然在以前的网络。

54. 发明申请

WO2008029819A3 SOFT DECISION GENERATION IN A LATTICE REDUCTION MIMO SYSTEM 审中-公开
标题翻译：减少MIMO系统中的软决策生成
公开(公告)号：WO2008029819A3
公开(公告)日：2008-05-02
申请号：PCT/JP2007067249
申请日：2007-08-29
申请人： TOSHIBA KK , PONNAMPALAM VISHAKAN , SANDELL MAGNUS STIG TORSTEN , LILLIE ANDREW GEORGE , MCNAMARA DARREN PHILLIP
发明人： PONNAMPALAM VISHAKAN , SANDELL MAGNUS STIG TORSTEN , LILLIE ANDREW GEORGE , MCNAMARA DARREN PHILLIP
IPC分类号： H04L25/06 , H04L25/03
CPC分类号： H04L25/067 , H04L25/03242
摘要： In a lattice-reduction-aided receiver based wireless communications system, soft estimates of transmitted bit values are determined from a received signal by applying lattice reduction to the channel estimate and equalising the received signal in accordance with the reduced basis channel, and determining probabilities of transmitted bits having particular values by generating a set of candidate vectors in the reduced basis based on nearest candidate vectors, determining a corresponding transmitted symbol vector for each candidate vector and, on the basis of the received signal determining the probability of each transmitted bit value having been transmitted.
摘要翻译：在基于格子减少辅助接收机的无线通信系统中，通过对信道估计应用网格约简并根据减小的基本信道对接收信号进行均衡，从接收信号确定发送比特值的软估计，并且确定通过基于最近的候选向量在减少的基础中生成一组候选向量来确定具有特定值的发送比特，确定每个候选向量的对应的发送符号向量，并且基于确定每个被发送的比特值的概率具有被传送。

55. 发明申请

WO2005098639A9 LOG IN SYSTEM AND METHOD 审中-公开
标题翻译：登录系统和方法
公开(公告)号：WO2005098639A9
公开(公告)日：2008-02-14
申请号：PCT/JP2005005384
申请日：2005-03-24
申请人： TOSHIBA KK , KASAHARA AKIHIRO , MIURA AKIRA , SUU HIROSHI , ISHIDA SHIGERU , NAKANO KAZUNORI
发明人： KASAHARA AKIHIRO , MIURA AKIRA , SUU HIROSHI , ISHIDA SHIGERU , NAKANO KAZUNORI
IPC分类号： G06F15/00 , G06K19/10 , G06F21/00 , G06F21/20 , G06K17/00 , H04L9/10 , H04L9/32
CPC分类号： G06F21/34
摘要： There are provided a log in system and method which can easily be applied to a corporation aggregate member and prevent unauthorized use of authentication information copied. Since log in is performed by using service right data (p11) for each medium identifier (SD-ID01) of a secure storage medium (SD), an unauthorized person who has copied authentication information cannot perform log in unless the unauthorized person uses the secure storage medium (SD). Moreover, when the secure storage medium is distributed to each person belonging to the corporation aggregate, it can be applied to the corporation aggregate user in the same way as to an individual user.
摘要翻译：提供了一种登录系统和方法，可以方便地应用于公司集合成员，并防止未经授权使用复制的认证信息。由于通过使用安全存储介质（SD）的每个介质标识符（SD-ID01）的服务权限数据（p11）来执行登录，所以复制认证信息的未经授权的人不能执行登录，除非未经授权的人使用安全的存储介质（SD）。此外，当将安全存储介质分配给属于公司集合的每个人时，其可以以与单个用户相同的方式应用于公司集合用户。

56. 发明申请

WO2007001081A3 METHOD , ARRAY , APPARATUS AND TEST SYSTEM TO DISCRIMINATE INDIVIDUALS 审中-公开
标题翻译：方法，阵列，装置和测试系统来区分个人
公开(公告)号：WO2007001081A3
公开(公告)日：2007-04-26
申请号：PCT/JP2006313198
申请日：2006-06-27
申请人： TOSHIBA KK , TAKAHASHI MASAYOSHI , HASHIMOTO KOJI
发明人： TAKAHASHI MASAYOSHI , HASHIMOTO KOJI
IPC分类号： C12Q1/68 , C12M1/00 , C12M1/38 , C12N15/09 , G01N33/53 , G01N37/00
CPC分类号： C12Q1/6827 , C12Q2565/607 , C12Q2565/518 , C12Q2535/131
摘要： The invention provides a method of individual discriminating. The method includes selecting and using single nucleotide polymorphism satisfying any one of the conditions defined by this invention.
摘要翻译：本发明提供了个体鉴别的方法。该方法包括选择和使用满足本发明定义的任一条件的单核苷酸多态性。

57. 发明申请

WO2006052021A3 LSI APPARATUS OPERATED BY OPTICAL CLOCK 审中-公开
标题翻译：光器件操作的LSI设备
公开(公告)号：WO2006052021A3
公开(公告)日：2006-11-09
申请号：PCT/JP2005021182
申请日：2005-11-11
申请人： TOSHIBA KK , FURUYAMA HIDETO
发明人： FURUYAMA HIDETO
IPC分类号： G06F1/10 , G02B6/43 , G06F1/04 , H01L27/15 , H01L31/12
CPC分类号： G06F1/105 , G02B6/125 , G02B6/4214
摘要： In an LSI system, a short optical pulse train is guided to an optical divider which divides the short optical pulse train into first and second short optical pulse trains. A retardation of 1/2 of the pulse period is produced between the first and second short optical pulse trains. The first and second short optical pulse trains are guided to first and second photodiodes on an LSI chip and are converted in the first and second electric current pulse trains, respectively. The first and second electric current pulse trains are supplied to an electrical clock output terminal electrically connected to the first and second photodiodes so that the electrical clock output terminals generates an electric clock pulse.
摘要翻译：在LSI系统中，将短光脉冲串引导到将短光脉冲串分割成第一和第二短光脉冲串的光分路器。在第一和第二短光脉冲串之间产生脉冲周期的1/2的延迟。第一和第二短光脉冲串被引导到LSI芯片上的第一和第二光电二极管，并分别在第一和第二电流脉冲串中转换。第一和第二电流脉冲串被提供给电连接到第一和第二光电二极管的电时钟输出端子，使得电时钟输出端子产生电时钟脉冲。

58. 发明申请

WO2006044901A3 TERMINAL TRANSMIT POWER CONTROL WITH LINK ADAPTATION 审中-公开
标题翻译：带链路适配的终端发射功率控制
公开(公告)号：WO2006044901A3
公开(公告)日：2006-09-21
申请号：PCT/US2005037458
申请日：2005-10-18
申请人： TOSHIBA KK , TELCORDIA TECH INC , MATSUO RYOKO , OBAYASHI SHUICHI , KODAMA TOSHIKAZU , FAMOLARI DAVID
发明人： MATSUO RYOKO , OBAYASHI SHUICHI , KODAMA TOSHIKAZU , FAMOLARI DAVID
IPC分类号： H04B7/005
CPC分类号： H04W52/24 , H04W24/00 , H04W28/22 , H04W52/146 , H04W52/22 , H04W52/267 , H04W52/46
摘要： Methods for coordinating power usage and link adaptation in wireless communications are described. Terminals and/or access points (APs) may attempt to modify terminals' transmit power in relation to a desired communication data transfer rate. Link adoption may also be used in conjunction with the described methods.
摘要翻译：描述了用于协调无线通信中的功率使用和链路自适应的方法。终端和/或接入点（AP）可以尝试相对于期望的通信数据传输速率修改终端的发射功率。链接的采用也可以与所描述的方法结合使用。

59. 发明申请

WO2006049740A3 METHOD FOR INTEGRATING MULTIPLE OBJECT FILES FROM HETEROGENEOUS ARCHITECTURES INTO A SET OF FILES 审中-公开
标题翻译：将多个异构体结构中的多个对象文件整合到一组文件中的方法
公开(公告)号：WO2006049740A3
公开(公告)日：2006-08-10
申请号：PCT/US2005034460
申请日：2005-09-23
申请人： SONY COMPUTER ENTERTAINMENT INC , IBM , TOSHIBA KK
发明人： CHOW ALEX CHUNGHEN , DAY MICHAEL NORMAN , GOWEN MICHAEL STAN , INOUE KEISUKE , XENIDIS JAMES , UCHIKAWA TAKAYUKI
IPC分类号： G06F9/445
CPC分类号： G06F8/54 , G06F9/4425
摘要： The present invention is a method for integrating multiple object codes from heterogeneous architectures. For a program on a first processor to reference a program from the name space of a second processor, the object code for the second-processor program is enclosed in a wrapper to create object code in the first-processor name space. The header of the wrapped object code defines a new symbol in the name space of the first processor, and the symbol points to the second-processor object code contained in the wrapped object code. Instead of directly referencing the second-processor object code, the referencing program on the first processor references the wrapped object code. A system tool can be used to wrap the object code which runs on the second processor.
摘要翻译：本发明是用于集成来自异构体系结构的多个目标代码的方法。对于第一个处理器上的程序从第二个处理器的名称空间引用程序，第二个处理器程序的目标代码封装在包装器中，以在第一个处理器名称空间中创建目标代码。包装目标代码的头文件在第一个处理器的名称空间中定义一个新符号，该符号指向包含在包装目标代码中的第二个处理器目标代码。第一处理器上的引用程序不是直接引用第二处理器对象代码，而是引用包装的对象代码。系统工具可以用来包装在第二个处理器上运行的目标代码。

60. 发明申请

WO2005124530A3 METHOD FOR CONTROLLING MEMORY CARD AND METHOD FOR CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY 审中-公开
标题翻译：用于控制存储卡的方法和用于控制非易失性半导体存储器的方法
公开(公告)号：WO2005124530A3
公开(公告)日：2006-05-26
申请号：PCT/JP2005011396
申请日：2005-06-15
申请人： TOSHIBA KK , ITO TAKAFUMI , SAKAMOTO HIROYUKI
发明人： ITO TAKAFUMI , SAKAMOTO HIROYUKI
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F3/0643 , G06F3/0613 , G06F3/0626 , G06F3/0679 , G06F12/0246 , G06F2212/7202
摘要： A method for controlling a memory card which includes a nonvolatile semiconductor memory whose memory area includes a plurality of write areas is disclosed. A first area which is a part of the plurality of write areas is set in accordance with management executed by a first file system. The first file system sequentially writes data along a direction in which addresses of the plurality of write areas increase. A second area which is a part of the plurality of write areas is set in accordance with management executed by a second file system. The second file system writes data in an order which does not depend on the addresses.
摘要翻译：一种用于控制存储卡的方法，其包括其存储区域包括多个写入区域的非易失性半导体存储器。根据由第一文件系统执行的管理来设置作为多个写入区域的一部分的第一区域。第一文件系统沿着多个写入区域的地址增加的方向顺序地写入数据。根据由第二文件系统执行的管理来设置作为多个写入区域的一部分的第二区域。第二个文件系统以不依赖于地址的顺序写入数据。

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