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71. 发明授权

US06639319B2 Conductive structure in an integrated circuit 有权
公开(公告)号：US06639319B2
公开(公告)日：2003-10-28
申请号：US09953675
申请日：2001-09-17
申请人： Jigish D. Trivedi , Ravi Iyer
发明人： Jigish D. Trivedi , Ravi Iyer
IPC分类号： H01L2348
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76846 , H01L21/7685 , H01L21/76855 , H01L21/76856 , H01L21/76864 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53257 , H01L29/456 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a local interconnect structure is provided. A first barrier layer comprising sputtered titanium nitride is formed over a topographical structure situated upon a field oxide region within a semiconductor substrate. A hard mask layer comprising tungsten silicide is formed over the first barrier layer. A photoresist layer is then formed over the hard mask layer. The hard mask layer is selectively removed from above an adjacent gate stack on the semiconductor substrate using an etch that is selective to the first barrier layer. The first barrier layer is selectively removed using an etch that is selective to the hard mask layer. A silica layer is formed over the hard mask layer. A recess is formed in the silica layer that is aligned with an active area within the semiconductor substrate. The recess is filled with an electrically conductive material. A second method of forming a local interconnect structure is provided comprising forming a first barrier layer comprising sputter titanium nitride over a semiconductor substrate having a topographical structure situated upon a field oxide region within the semiconductor substrate. A first electrically conductive layer comprising tungsten is then formed over the first barrier layer using chemical vapor deposition. The first electrically conductive layer provides good step coverage over the topographical structure. A second barrier layer comprising sputtered titanium nitride is formed over the first electrically conductive layer. A hard mask layer comprising polysilicon or silica is then formed over the second barrier layer. The hard mask is selectively removed from above an adjacent gate stack on the semiconductor substrate with an etch that is selective to the second barrier layer. The second barrier layer, the first conductive layer, and the first barrier layer are selectively removed, thereby exposing the underlying gate stack on the semiconductor substrate using a chemical etch selective to the hard mask layer. A silica layer is then formed with a recess therein that is filled with an electrically conductive material to form an active area contact through the local interconnect structure.

72. 发明授权

US06570252B1 Integrated circuitry 有权
标题翻译：集成电路
公开(公告)号：US06570252B1
公开(公告)日：2003-05-27
申请号：US09263029
申请日：1999-03-05
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76846 , H01L21/7685
摘要： In one aspect, the invention includes a semiconductor device comprising: a) an electrically insulative layer over a substrate; b) an opening within the electrically insulative layer, the opening having a periphery defined at least in part by a bottom surface and a sidewall surface; c) a first layer comprising TiN within the opening, the first layer being over the bottom surface and along the sidewall surface; d) a second layer comprising elemental Ti over the electrically insulative layer but substantially not within the opening, the second layer having a thickness of less than 75Å along the sidewall surface and over the bottom surface; and e) an aluminum-comprising layer within the opening and over the second layer. In another aspect, the invention includes a semiconductor device comprising: a) a first aluminum-comprising layer over an electrically insulative layer; b) a first titanium-comprising layer over the first aluminum-comprising layer; c) a second titanium-comprising layer over the first titanium-comprising layer, one of the first and second titanium-comprising layers comprising elemental Ti and the other of the first and second titanium-comprising layers comprising TiN; and d) a second aluminum-comprising layer over the second titanium-comprising layer.
摘要翻译：一方面，本发明包括半导体器件，其包括：a）在衬底上的电绝缘层; b）电绝缘层内的开口，所述开口具有至少部分地由底表面和侧壁表面限定的周边; c）在所述开口内包含TiN的第一层，所述第一层在所述底表面上并沿着所述侧壁表面; d）在电绝缘层上但基本上不在开口内的包含元素Ti的第二层，第二层沿侧壁表面和底表面具有小于75埃的厚度; 以及e）在所述开口内和所述第二层上方的含铝层。在另一方面，本发明包括半导体器件，其包括：a）在电绝缘层上的第一含铝层; b）在第一含铝层上的第一含钛层; c）在所述第一含钛层上的第二含钛层，所述第一和第二含钛层中的一个包含元素Ti，所述第一和第二含钛层中的另一个包含TiN; 和d）在所述第二含钛层上的第二含铝层。

73. 发明授权

US06462394B1 Device configured to avoid threshold voltage shift in a dielectric film 失效
标题翻译：器件被配置为避免电介质膜中的阈值电压偏移
公开(公告)号：US06462394B1
公开(公告)日：2002-10-08
申请号：US09312373
申请日：1999-05-13
申请人： Randhir P. S. Thakur , Ravi Iyer , Howard Rhodes
发明人： Randhir P. S. Thakur , Ravi Iyer , Howard Rhodes
IPC分类号： H01L2900
CPC分类号： H01L23/564 , H01L21/3144 , H01L21/76828 , H01L21/76829 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.
摘要翻译：提供了一种制造具有降低的阈值电压偏移的集成电路的方法。在半导体衬底上形成非导电区域，在半导体衬底上形成有源区域。有源区由非导电区分开。势垒层和电介质层沉积在非导电区域上并在有源区上方。对集成电路施加热量，导致阻挡层退火。

74. 发明授权

US06423631B1 Isolation using an antireflective coating 有权
标题翻译：使用抗反射涂层进行隔离
公开(公告)号：US06423631B1
公开(公告)日：2002-07-23
申请号：US09625164
申请日：2000-07-25
申请人： Ravi Iyer , Steven M. McDonald , Thomas R. Glass , Zhiping Yin
发明人： Ravi Iyer , Steven M. McDonald , Thomas R. Glass , Zhiping Yin
IPC分类号： H01L214763
CPC分类号： G03F7/091 , G03F7/092 , H01L21/0276 , H01L21/32 , H01L21/76202 , Y10T428/24471 , Y10T428/24917
摘要： A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer. The antireflective material layer may include a layer of material selected from the group of silicon nitride, silicon oxide, and silicon oxynitride and further may be a silicon-rich layer. The oxidation diffusion barrier stacks may be used for oxidation of field regions for isolation in an integration circuit. Further, the various oxidation diffusion barrier stacks are also described.
摘要翻译：形成用于集成电路制造的氧化扩散阻挡层叠体的方法包括在半导体衬底组件上形成无机抗反射材料层，然后在无机抗反射材料层上形成氧化扩散阻挡层。形成这种堆叠的另一种方法包括在半导体衬底组件上形成衬垫氧化物层，然后在衬垫氧化物层上形成无机抗反射材料层，形成在抗反射材料层上的氧化扩散阻挡层。形成叠层的另一种方法包括在半导体衬底组件上形成焊盘氧化物层。然后在焊盘氧化物层上形成第一氧化扩散阻挡层，在第一氧化扩散阻挡层上形成无机抗反射材料层，在无机抗反射材料层上形成第二氧化扩散阻挡层。抗反射材料层可以包括选自氮化硅，氧化硅和氮氧化硅的材料层，并且还可以是富硅层。氧化扩散阻挡层可以用于场集成电路中用于隔离的场区氧化。此外，还描述了各种氧化扩散阻挡层叠体。

75. 发明授权

US06297175B1 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers 失效
公开(公告)号：US06297175B1
公开(公告)日：2001-10-02
申请号：US09548491
申请日：2000-04-13
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： C23C1640
CPC分类号： H01L21/02164 , C03C17/02 , C23C16/0245 , C23C16/0272 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/31612 , H01L21/76826 , H01L21/76834 , H01L21/76837
摘要： A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 is disclosed. The entire method, which can be performed in a single cluster tool and even in a single chamber, begins by placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber. A “clean” silicate glass base layer that is substantially free of carbon particle impurities on an upper surface is then formed on the wafer surface in one of two ways. The first employs plasma-enhanced chemical vapor deposition using TEOS and diatomic oxygen gases as precursors to first deposit a “dirty” silicate glass base layer having carbon particle impurities imbedded on an upper surface thereof. The dirty base layer is then transformed to a clean base layer by subjecting it to a plasma treatment, which involves flowing a mixture of a diamagnetic oxygen-containing oxidant, such as ozone or hydrogen peroxide, and diatomic oxygen gas into the chamber and striking an RF plasma at a power density setting of about 0.25 to 3.0 watts/cm2 for a period of from 30-300 seconds. It is hypothesized that the plasma treatment burns off the impurities, which are present in the PECVD-deposited base layer and which may be responsible for certain hydrophilic surface effects which repel TEOS molecules. The plasma treatment also creates a high degree of surface uniformity on the PECVD-deposited glass layer. The second way of forming a clean silicate glass base layer involves flowing hydrogen peroxide vapor and at least one gaseous compound selected from the group consisting of silane and disilane into the deposition chamber. Following the formation of the clean base layer, a subsequent glass layer is deposited over the PECVD-deposited glass layer in the same chamber or cluster tool using chemical vapor deposition and TEOS and ozone as precursor compounds.

76. 发明授权

US06255212B1 Method of making a void-free aluminum film 有权
标题翻译：制造无空隙铝膜的方法
公开(公告)号：US06255212B1
公开(公告)日：2001-07-03
申请号：US09294771
申请日：1999-04-19
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L2144
CPC分类号： H01L23/53223 , H01L21/76847 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method for depositing an aluminum film limits the growth of voids and notches in the aluminum film and forms and aluminum film with a reduced amount of voids and notches. The first step of the method is to form an underlying layer upon which is deposited an aluminum film having a first thickness. The surface of the aluminum film is then exposed to a passivation species which coats the aluminum grains and precipitates at the grain boundaries so as to prevent grain movement. The exposure of the aluminum film to the passivation species reduces void formation and coalescence of the voids. An aluminum layer having a second thickness is then deposited over the initially deposited aluminum layer. In a second embodiment of the invention, the passivation species is deposited with MOCVD and to form an electromigration-resistant alloy. A third embodiment involves multiple depositions of aluminum, with exposure to a passivation species conducted after each deposition. Each deposition is also conducted at a successively lower temperature than the prior deposition.
摘要翻译：铝膜的沉积方法限制了铝膜中的空隙和凹口的生长，并形成了具有减少量的空隙和凹口的铝膜。该方法的第一步是形成下层，沉积具有第一厚度的铝膜。然后将铝膜的表面暴露于钝化物质，其涂覆铝颗粒并在晶界处沉淀，以防止颗粒移动。铝膜暴露于钝化物质可以减少空隙的形成和孔隙的聚结。然后在初始沉积的铝层上沉积具有第二厚度的铝层。在本发明的第二个实施方案中，钝化物质用MOCVD沉积并形成耐电迁移合金。第三个实施例涉及铝的多次沉积，暴露于在每次沉积之后进行的钝化物质。每次沉积也在比先前的沉积相继低的温度下进行。

77. 发明授权

US06251807B1 Method for improving thickness uniformity of deposited ozone-teos silicate glass layers 有权
公开(公告)号：US06251807B1
公开(公告)日：2001-06-26
申请号：US09548572
申请日：2000-04-13
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , C03C17/02 , C23C16/0245 , C23C16/0272 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/31612 , H01L21/76826 , H01L21/76834 , H01L21/76837
摘要： A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 is disclosed. The entire method, which can be performed in a single cluster tool and even in a single chamber, begins by placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber. A “clean” silicate glass base layer that is substantially free of carbon particle impurities on an upper surface is then formed on the wafer surface in one of two ways. The first employs plasma-enhanced chemical vapor deposition using TEOS and diatomic oxygen gases as precursors to first deposit a “dirty” silicate glass base layer having carbon particle impurities imbedded on an upper surface thereof. The dirty base layer is then transformed to a clean base layer by subjecting it to a plasma treatment, which involves flowing a mixture of a diamagnetic oxygen-containing oxidant, such as ozone or hydrogen peroxide, and diatomic oxygen gas into the chamber and striking an RF plasma at a power density setting of about 0.25 to 3.0 watts/cm2 for a period from 30-300 seconds. It is hypothesized that the plasma treatment burns off the impurities, which are present in the PECVD-deposited base layer and which may be responsible for certain hydrophilic surface effects which repel TEOS molecules. The plasma treatment also creates a high degree of surface uniformity on the PECVD-deposited glass layer. The second way of forming a clean silicate glass base layer involves flowing hydrogen peroxide vapor and at least one gaseous compound selected from the group consisting of silane and disilane into the deposition chamber. Following the formation of the clean base layer, a subsequent glass layer is deposited over the PECVD-deposited glass layer in the same chamber or cluster tool using chemical vapor deposition and TEOS and ozone as precursor compounds.

78. 发明授权

US6107686A Interlevel dielectric structure 有权
标题翻译：电介质结构
公开(公告)号：US6107686A
公开(公告)日：2000-08-22
申请号：US249659
申请日：1999-02-12
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

79. 发明授权

US6107214A Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers 有权
公开(公告)号：US6107214A
公开(公告)日：2000-08-22
申请号：US222565
申请日：1998-12-29
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： C03C17/02 , C23C16/02 , C23C16/40 , C23C16/56 , H01L21/316 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02164 , C03C17/02 , C23C16/0245 , C23C16/0272 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/31612 , H01L21/76826 , H01L21/76834 , H01L21/76837
摘要： A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O.sub.3 is disclosed. The entire method, which can be performed in a single cluster tool and even in a single chamber, begins by placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber. A "clean" silicate glass base layer that is substantially free of carbon particle impurities on an upper surface is then formed on the wafer surface in one of two ways. The first employs plasma-enhanced chemical vapor deposition using TEOS and diatomic oxygen gases as precursors to first deposit a "dirty" silicate glass base layer having carbon particle impurities imbedded on an upper surface. The dirty base layer is then transformed to a clean base layer by subjecting it to a plasma treatment, which involves flowing a mixture of a diamagnetic oxygen-containing oxidant, such as ozone or hydrogen peroxide, and diatomic oxygen gas into the chamber and striking an RF plasma at a power density setting of about 0.25 to 3.0 watts/cm.sup.2 for a period of from 30-300 seconds. It is hypothesized that the plasma treatment burns off the impurities, which are present in the PECVD-deposited base layer and which may be responsible for certain hydrophilic surface effects which repel TEOS molecules. The plasma treatment also creates a high degree of surface uniformity on the PECVD-deposited glass layer. The second way of forming a clean silicate glass base layer involves flowing hydrogen peroxide vapor and at least one gaseous compound selected from the group consisting of silane and disilane into the deposition chamber. Following the formation of the clean base layer, a subsequent glass layer is deposited over the PECVD-deposited glass layer in the same chamber or cluster tool using chemical vapor deposition and TEOS and ozone as precursor compounds.

80. 发明授权

US6107183A Method of forming an interlevel dielectric 失效
标题翻译：形成层间电介质的方法
公开(公告)号：US6107183A
公开(公告)日：2000-08-22
申请号：US677514
申请日：1996-07-10
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes forming first and second dielectric layers between which are located lines of a conductive material that are also formed with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括形成第一和第二电介质层，它们之间位于导电材料的定位线之间，导电材料的导电材料线之间的空间中还形成介电材料，电介质材料的下表面延伸低于下部电介质材料与其相邻的导电材料的线的表面，并且电介质材料的上表面比与其相邻的导电材料的上表面延伸，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

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