专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06822328B2 Integrated circuitry 有权
标题翻译：集成电路
公开(公告)号：US06822328B2
公开(公告)日：2004-11-23
申请号：US10229865
申请日：2002-08-27
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76846 , H01L21/7685
摘要： The invention includes integrated circuitry having an electrically insulative layer over a substrate and an opening within the electrically insulative layer. The opening has a periphery defined at least in part by a bottom surface and a sidewall surface. A first titanium layer is disposed within the opening in contact with the bottom surface and is thicker along the bottom surface than along the sidewall. A layer of TiN is provided over the first titanium layer along the bottom surface and along the sidewall surface of the opening, and a second layer of titanium is disposed over the electrically insulative layer but substantially not within the opening. The second titanium layer has a thickness of less then 50 Å along the sidewall surface and over the bottom surface. An aluminum-comprising layer is within the opening and over the second layer.
摘要翻译：本发明包括在基板上具有电绝缘层的集成电路和电绝缘层内的开口。开口具有至少部分地由底表面和侧壁表面限定的外围。第一钛层设置在与底表面接触的开口内，并且沿着底表面比沿侧壁更厚。沿着底表面并沿着开口的侧壁表面在第一钛层上提供TiN层，并且第二层钛层设置在电绝缘层上，但基本上不在开口内。第二钛层的侧壁表面和底面的厚度小于50埃。包含铝的层在开口内和第二层之上。

2. 发明授权

US5985770A Method of depositing silicon oxides 失效
公开(公告)号：US5985770A
公开(公告)日：1999-11-16
申请号：US915987
申请日：1997-08-21
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： C23C16/30 , H01L21/316 , H01L21/368
CPC分类号： H01L21/02271 , C23C16/30 , H01L21/02126 , H01L21/02129 , H01L21/02131 , H01L21/0214 , H01L21/31612
摘要： The invention comprises methods of depositing silicon oxide material onto a substrate. In but one aspect of the invention, a method of depositing a silicon oxide containing layer on a substrate includes initially forming a layer comprising liquid silicon oxide precursor onto a substrate. After forming the layer, the layer is doped and transformed into a solid doped silicon oxide containing layer on the substrate. In a preferred implementation, the doping is by gas phase doping and the liquid precursor comprises Si(OH).sub.4. In the preferred implementation, the transformation occurs by raising the temperature of the deposited liquid precursor to a first elevated temperature and polymerizing the deposited liquid precursor on the substrate. The temperature is continued to be raised to a second elevated temperature higher than the first elevated temperature and a solid doped silicon oxide containing layer is formed on the substrate.

3. 发明授权

US5963835A Method of forming aluminum film 失效
标题翻译：铝膜成型方法
公开(公告)号：US5963835A
公开(公告)日：1999-10-05
申请号：US977786
申请日：1997-11-25
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L23/485 , H01L23/532 , H01L21/70
CPC分类号： H01L23/53223 , H01L23/485 , H01L2924/0002
摘要： A method for depositing an aluminum film limits the growth of voids and notches in the aluminum film and forms and aluminum film with a reduced amount of voids and notches. The first step of the method is to form an underlying layer upon which is deposited an aluminum film having a first thickness. The surface of the aluminum film is then exposed to a passivation species which coats the aluminum grains and precipitates at the grain boundaries so as to prevent grain movement. The exposure of the aluminum film to the passivation species reduces void formation and coalescence of the voids. An aluminum layer having a second thickness is then deposited over the initially deposited aluminum layer. In a second embodiment of the invention, the passivation species is deposited with MOCVD and to form an electromigration-resistant alloy. A third embodiment involves multiple depositions of aluminum, with exposure to a passivation species conducted after each deposition. Each deposition is also conducted at a successively lower temperature than the prior deposition.
摘要翻译：铝膜的沉积方法限制了铝膜中的空隙和凹口的生长，并形成了具有减少量的空隙和凹口的铝膜。该方法的第一步是形成下层，沉积具有第一厚度的铝膜。然后将铝膜的表面暴露于钝化物质，其涂覆铝颗粒并在晶界处沉淀，以防止颗粒移动。铝膜暴露于钝化物质可以减少空隙的形成和孔隙的聚结。然后在初始沉积的铝层上沉积具有第二厚度的铝层。在本发明的第二个实施方案中，钝化物质用MOCVD沉积并形成耐电迁移合金。第三个实施例涉及铝的多次沉积，暴露于在每次沉积之后进行的钝化物质。每次沉积也在比先前的沉积相继低的温度下进行。

4. 发明授权

US5824365A Method of inhibiting deposition of material on an internal wall of a chemical vapor deposition reactor 失效
标题翻译：抑制材料沉积在化学气相沉积反应器的内壁上的方法
公开(公告)号：US5824365A
公开(公告)日：1998-10-20
申请号：US668855
申请日：1996-06-24
申请人： Gurtej S. Sandhu , Ravi Iyer , Donald L. Westmoreland
发明人： Gurtej S. Sandhu , Ravi Iyer , Donald L. Westmoreland
IPC分类号： C23C16/44 , B05D7/22 , C23C16/00
CPC分类号： C23C16/4404
摘要： A method of inhibiting deposition of material on a wall of a chemical vapor deposition reactor includes providing a chemical vapor deposition reactor having a wall which has an inside facing surface, the inside facing surface at least partially defining a chemical vapor deposition reactor chamber; forming a first material atop the inside facing surface; positioning a substrate in the chemical vapor deposition reactor chamber, the substrate having an outer surface; and chemical vapor depositing a second material layer on the substrate in a manner which is selective to the substrate outer surface, and not the first material, thereby restricting deposition of the second layer on the reactor inside facing surface.
摘要翻译：一种抑制材料沉积在化学气相沉积反应器的壁上的方法包括提供具有壁的化学气相沉积反应器，所述壁具有面向内的表面，所述内表面至少部分地限定化学气相沉积反应室; 在面向内表面的顶部形成第一材料; 将衬底定位在化学气相沉积反应器室中，所述衬底具有外表面; 以及以对衬底外表面有选择性的方式在衬底上沉积第二材料层，而不是第一材料，由此限制第二层在反应器面对表面上的沉积。

5. 发明授权

US07763327B2 Methods using ozone for CVD deposited films 失效
标题翻译：臭氧用于CVD沉积膜的方法
公开(公告)号：US07763327B2
公开(公告)日：2010-07-27
申请号：US11192326
申请日：2005-07-27
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： B05D3/06
CPC分类号： C23C16/401
摘要： A CVD ozone (O3) deposition process, with the preferred embodiment comprising the steps of disposing a substrate in a chemical vapor deposition chamber and exposing the substrate surface to a SiO2 precursor gas, a carrier gas, and optionally a dopant gas in the presence of ozone and exposing the reaction volume of the 5 gases above the substrate surface to a high intensity light source, to increase the functional atomic oxygen concentration and reduce the fixed charge in the deposited films.
摘要翻译： CVD臭氧（O3）沉积方法，优选实施方案包括以下步骤：在化学气相沉积室中设置衬底，并将衬底表面暴露于SiO 2前体气体，载气和任选的掺杂气体中，臭氧，并将基板表面上方的5种气体的反应体积暴露于高强度光源，以增加功能原子氧浓度并降低沉积膜中的固定电荷。

6. 发明授权

US07112542B2 Methods of forming materials between conductive electrical components, and insulating materials 有权
标题翻译：在导电电气部件和绝缘材料之间形成材料的方法
公开(公告)号：US07112542B2
公开(公告)日：2006-09-26
申请号：US10330719
申请日：2002-12-27
申请人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
发明人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
IPC分类号： H01L21/31 , H01L21/469 , H01L21/76
CPC分类号： H01L21/7682 , H01L21/02115 , H01L21/02118 , H01L21/02167 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/02362 , H01L21/31695 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , Y10T428/12014 , Y10T428/24149 , Y10T428/249921 , Y10T428/25 , Y10T428/259 , H01L2924/00
摘要： Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. Other methods include forming a material between a pair of conductive electrical components comprising: forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. Some embodiments include an insulating material adjacent a conductive electrical component, such material comprising a matrix and at least one void within the matrix.
摘要翻译：在导电元件之间形成绝缘材料的方法包括形成邻近导电电气部件的材料，该材料包括：部分蒸发物质以形成邻近导电电气部件的基体，所述基体在其内具有至少一个空隙。其他方法包括在一对导电电气部件之间形成材料，包括：在一个质量块内形成一对导电的电气部件，并由该质量块的一大片分隔; 在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及使所述质量块的膨胀程度有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙。一些实施例包括邻近导电电气部件的绝缘材料，这种材料包括基质和基质内的至少一个空隙。

7. 发明授权

US06570252B1 Integrated circuitry 有权
标题翻译：集成电路
公开(公告)号：US06570252B1
公开(公告)日：2003-05-27
申请号：US09263029
申请日：1999-03-05
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76846 , H01L21/7685
摘要： In one aspect, the invention includes a semiconductor device comprising: a) an electrically insulative layer over a substrate; b) an opening within the electrically insulative layer, the opening having a periphery defined at least in part by a bottom surface and a sidewall surface; c) a first layer comprising TiN within the opening, the first layer being over the bottom surface and along the sidewall surface; d) a second layer comprising elemental Ti over the electrically insulative layer but substantially not within the opening, the second layer having a thickness of less than 75Å along the sidewall surface and over the bottom surface; and e) an aluminum-comprising layer within the opening and over the second layer. In another aspect, the invention includes a semiconductor device comprising: a) a first aluminum-comprising layer over an electrically insulative layer; b) a first titanium-comprising layer over the first aluminum-comprising layer; c) a second titanium-comprising layer over the first titanium-comprising layer, one of the first and second titanium-comprising layers comprising elemental Ti and the other of the first and second titanium-comprising layers comprising TiN; and d) a second aluminum-comprising layer over the second titanium-comprising layer.
摘要翻译：一方面，本发明包括半导体器件，其包括：a）在衬底上的电绝缘层; b）电绝缘层内的开口，所述开口具有至少部分地由底表面和侧壁表面限定的周边; c）在所述开口内包含TiN的第一层，所述第一层在所述底表面上并沿着所述侧壁表面; d）在电绝缘层上但基本上不在开口内的包含元素Ti的第二层，第二层沿侧壁表面和底表面具有小于75埃的厚度; 以及e）在所述开口内和所述第二层上方的含铝层。在另一方面，本发明包括半导体器件，其包括：a）在电绝缘层上的第一含铝层; b）在第一含铝层上的第一含钛层; c）在所述第一含钛层上的第二含钛层，所述第一和第二含钛层中的一个包含元素Ti，所述第一和第二含钛层中的另一个包含TiN; 和d）在所述第二含钛层上的第二含铝层。

8. 发明授权

US06255212B1 Method of making a void-free aluminum film 有权
标题翻译：制造无空隙铝膜的方法
公开(公告)号：US06255212B1
公开(公告)日：2001-07-03
申请号：US09294771
申请日：1999-04-19
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L2144
CPC分类号： H01L23/53223 , H01L21/76847 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method for depositing an aluminum film limits the growth of voids and notches in the aluminum film and forms and aluminum film with a reduced amount of voids and notches. The first step of the method is to form an underlying layer upon which is deposited an aluminum film having a first thickness. The surface of the aluminum film is then exposed to a passivation species which coats the aluminum grains and precipitates at the grain boundaries so as to prevent grain movement. The exposure of the aluminum film to the passivation species reduces void formation and coalescence of the voids. An aluminum layer having a second thickness is then deposited over the initially deposited aluminum layer. In a second embodiment of the invention, the passivation species is deposited with MOCVD and to form an electromigration-resistant alloy. A third embodiment involves multiple depositions of aluminum, with exposure to a passivation species conducted after each deposition. Each deposition is also conducted at a successively lower temperature than the prior deposition.
摘要翻译：铝膜的沉积方法限制了铝膜中的空隙和凹口的生长，并形成了具有减少量的空隙和凹口的铝膜。该方法的第一步是形成下层，沉积具有第一厚度的铝膜。然后将铝膜的表面暴露于钝化物质，其涂覆铝颗粒并在晶界处沉淀，以防止颗粒移动。铝膜暴露于钝化物质可以减少空隙的形成和孔隙的聚结。然后在初始沉积的铝层上沉积具有第二厚度的铝层。在本发明的第二个实施方案中，钝化物质用MOCVD沉积并形成耐电迁移合金。第三个实施例涉及铝的多次沉积，暴露于在每次沉积之后进行的钝化物质。每次沉积也在比先前的沉积相继低的温度下进行。

9. 发明授权

US6091150A Integrated circuitry comprising electrically insulative material over interconnect line tops, sidewalls and bottoms 有权
标题翻译：集成电路，包括互连线顶部，侧壁和底部上的电绝缘材料
公开(公告)号：US6091150A
公开(公告)日：2000-07-18
申请号：US272060
申请日：1999-03-18
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76838 , H01L23/5222 , H01L2924/0002
摘要： A semiconductor processing method of forming an electrically conductive interconnect line having an electrical conductive covering predominately coextensive therewith, includes, a) providing an conductive interconnect line over a first electrically insulating material, the line having a top and sidewalls; b) selectively depositing a second electrically insulating material layer over the interconnect line and the first insulating material in a manner which deposits a greater thickness of the second insulating material atop the interconnect line than a thickness of the second insulating material over the first insulating material; c) anisotropically etching the second insulating material layer inwardly to at least the first insulating material yet leaving second insulating material over the top and the sidewalls of the interconnect line; and d) providing an electrically conductive layer over the anisotropically etched second insulating layer to form a conductive layer which is predominately coextensive with the interconnect line over the etched second insulating material. The method further comprises provision of a base electrically conductive layer beneath the first insulating material, with the anisotropically etching step etching through the first insulating material to the base conductive layer, and the conductive layer being provided in electrical connection with the base conductive layer. Integrated circuitry produced by the method and other methods is also disclosed.
摘要翻译：一种形成具有与其主要共同延伸的导电覆盖层的导电互连线的半导体处理方法包括：a）在第一电绝缘材料上提供导电互连线，该线具有顶部和侧壁; b）在所述互连线和所述第一绝缘材料上选择性地沉积第二电绝缘材料层，所述第二电绝缘材料层以在所述互连线上方沉积更大厚度的所述第二绝缘材料的厚度大于所述第一绝缘材料上所述第二绝缘材料的厚度; c）将第二绝缘材料层向内各向异性地蚀刻至少至少第一绝缘材料，同时将第二绝缘材料留在互连线的顶部和侧壁上; 以及d）在各向异性蚀刻的第二绝缘层上方设置导电层，以形成导电层，该导电层与蚀刻的第二绝缘材料上的互连线主要共同延伸。该方法还包括在第一绝缘材料下面提供基底导电层，各向异性蚀刻步骤通过第一绝缘材料蚀刻到基底导电层，并且导电层设置为与基底导电层电连接。还公开了通过该方法和其它方法生产的集成电路。

10. 发明授权

US5735960A Apparatus and method to increase gas residence time in a reactor 失效
标题翻译：在反应器中增加气体停留时间的装置和方法
公开(公告)号：US5735960A
公开(公告)日：1998-04-07
申请号：US627677
申请日：1996-04-02
申请人： Gurtej S. Sandhu , Ravi Iyer , Sujit Sharan
发明人： Gurtej S. Sandhu , Ravi Iyer , Sujit Sharan
IPC分类号： C23C16/44 , C23C16/455 , C23C16/509 , C23C16/00
CPC分类号： C23C16/45517 , C23C16/4412 , C23C16/455 , C23C16/45591 , C23C16/509
摘要： An apparatus is provided for controlling the flow of gaseous reactants in a CVD reactor through the use of a body having interior and exterior regions, in which the body defines at least one flow path between the interior and exterior regions so as to create a pressure drop from the interior to the exterior of the body within the chamber. The body is disposed in a reaction chamber with a first area proximate a gaseous reactant inlet and a second area proximate a substrate support such that the substrate is positioned in proximity to the interior of the body. As such, gaseous reactants introduced into the interior of said chamber through the inlet create a pressure drop between the interior and the exterior of the body. In a preferred embodiment, the body is cylindrically shaped and contains perforations providing the flow paths. Preferably, the perforations are either more numerous or larger in the second area than the first area to create a pressure gradient in the interior of the body. Alternatively, the perforations may be uniform in size and uniformly distributed over the body or the perforations can be configured to create a desired pressure differential in the body to support a plasma created in the body and control its location.
摘要翻译：提供了一种用于通过使用具有内部和外部区域的主体来控制CVD反应器中的气态反应物的流动的装置，其中主体限定了内部和外部区域之间的至少一个流动路径，以便产生压降从室内的内部到外部。身体设置在具有接近气体反应物入口的第一区域和接近基底支撑件的第二区域的反应室中，使得基底定位在身体内部附近。因此，通过入口引入所述室的内部的气态反应物在主体的内部和外部之间产生压降。在优选实施例中，主体是圆柱形的并且包含提供流动路径的穿孔。优选地，穿孔在第二区域中比第一区域更多或更大，以在身体的内部产生压力梯度。或者，穿孔的尺寸可以是均匀的并且均匀地分布在身体上，或者穿孔可以被配置成在身体中产生期望的压力差，以支撑在体内产生的等离子体并控制其位置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式