会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 73. 发明申请
    • System and method of controlling power in a multi-threaded processor
    • 在多线程处理器中控制电源的系统和方法
    • US20060294520A1
    • 2006-12-28
    • US11167973
    • 2005-06-27
    • William Anderson
    • William Anderson
    • G06F9/46
    • G06F9/3851G06F1/3203G06F9/4812
    • A multithreaded processor device is disclosed and includes a plurality of execution units to execute a plurality of program threads and includes a global low power detection circuit. The global low power detection circuit includes an input that is responsive to each of the plurality of program threads. The input indicates an execution activity level for each of the plurality of program threads. The global low power detection circuit further comprises logic to evaluate the activity level of each of the plurality of program threads. The logic provides a power level signal. Additionally, the global low power detection circuit includes an output that is responsive to the power level signal. The output is coupled to one or more global resources within the multithreaded processor and the output selectively controls an amount of power provided to the one or more global resources.
    • 公开了一种多线程处理器设备,并且包括执行多个程序线程的多个执行单元,并且包括全局低功率检测电路。 全局低功率检测电路包括响应于多个程序线程中的每一个的输入。 输入指示多个程序线程中的每一个的执行活动级别。 全局低功率检测电路还包括用于评估多个程序线程中的每一个的活动级别的逻辑。 该逻辑提供功率电平信号。 另外,全局低功率检测电路包括响应于功率电平信号的输出。 输出耦合到多线程处理器内的一个或多个全局资源,并且输出选择性地控制提供给一个或多个全局资源的功率量。
    • 74. 发明申请
    • Instruction memory unit and method of operation
    • 指令存储单元和操作方法
    • US20060230259A1
    • 2006-10-12
    • US11104115
    • 2005-04-11
    • Muhammad AhmedLucian CodrescuErich PlondkeWilliam AndersonRobert LesterPhillip Jones
    • Muhammad AhmedLucian CodrescuErich PlondkeWilliam AndersonRobert LesterPhillip Jones
    • G06F9/00
    • G06F9/325G06F9/3802G06F9/3804G06F9/381
    • An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.
    • 指令存储单元包括可操作以存储程序指令的第一存储器结构,以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。 如果前向分支指令的分辨率与其最后一个分辨率相同,则第二存储器结构可操作以识别正向程序重定向构造的重复发出,并发出已经存储在第二存储器结构中的下一个程序指令。 第二存储器结构还可操作以发出反向程序重定向结构,确定目标指令是否存储在第二存储器结构中,如果目标指令存储在第二存储器结构中,则发出目标指令,并从 如果目标指令没有存储在第二存储器结构中的第一存储器结构。