专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20160142058A1 DELAY CIRCUIT 有权
标题翻译：延时电路
公开(公告)号：US20160142058A1
公开(公告)日：2016-05-19
申请号：US14796933
申请日：2015-07-10
申请人： SK hynix Inc.
发明人： Yo-Sep LEE
IPC分类号： H03K23/40 , H03K5/135
CPC分类号： H03K5/135 , H03K23/66 , H03K2005/00241 , H03K2005/00293
摘要： A delay circuit may include a fine timing measurement unit suitable for measuring fine timing information on whether an input signal corresponds to the timing of any one of an even cycle or an odd cycle based on a clock, a coarse delay unit suitable for delaying the input signal whose fine timing has been measured by the fine timing measurement unit in synchronization with a frequency divided clock and outputting a delayed signal, and a fine timing application unit suitable for applying the fine timing information to the delayed signal of the coarse delay unit.
摘要翻译：延迟电路可以包括适合于测量关于输入信号是否对应于基于时钟的偶数周期或奇数周期中的任一个的定时的精细定时信息的精细定时测量单元，适于延迟输入的粗延迟单元信号，其精细定时由精细定时测量单元与分频时钟同步并输出延迟信号，精度定时应用单元适用于将精细定时信息应用于粗延迟单元的延迟信号。

82. 发明申请

US20160118990A1 AUTOMATICALLY PLACED-AND-ROUTED ADPLL WITH PWM-BASED DCO RESOLUTION ENHANCEMENT 有权
标题翻译：基于PWM的DCO分辨率增强自动布置和布线
公开(公告)号：US20160118990A1
公开(公告)日：2016-04-28
申请号：US14894483
申请日：2014-05-31
申请人： THE REGENTS OF THE UNIVERSITY OF MICHIGAN
发明人： Muhammad FAISAL , David D. WENTZLOFF
IPC分类号： H03L7/099
CPC分类号： H03L7/0997 , H03K5/134 , H03K2005/00241 , H03L7/091 , H03L7/0995 , H03L7/103 , H03L2207/06 , H03L2207/50
摘要： An all digital phase-locked loop (PLL) and a method of controlling the PLL is provided. The method includes the steps of receiving a reference signal (fREF) at a controller and a time-to-digital converter (TDC), the controller and TDC being coupled to multiple tunable delay elements; receiving at the multiple tunable delay elements a first signal input via the controller and a pulse-width modulation (PWM) circuit; providing an PLL output (fDCO) to the TDC at least partially based on the first signal input; and generating a phase error output (ΦERR) based on the reference signal (fREF) and the PLL output (fDCO), wherein the phase error output (ΦERR) is provided as feedback to the controller to control the PLL output (fDCO).
摘要翻译：提供全数字锁相环（PLL）和控制PLL的方法。该方法包括以下步骤：在控制器和时间 - 数字转换器（TDC）处接收参考信号（fREF），所述控制器和TDC耦合到多个可调延迟元件; 在所述多个可调延迟元件处接收经由所述控制器输入的第一信号和脉冲宽度调制（PWM）电路; 至少部分地基于第一信号输入向TDC提供PLL输出（fDCO）; 以及基于参考信号（fREF）和PLL输出（fDCO）产生相位误差输出（ΦERR），其中相位误差输出（ΦERR）被提供给控制器以控制PLL输出（fDCO）。

83. 发明授权

US09319040B2 Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signals 有权
标题翻译：分配多路复用逻辑，以消除可变时钟周期，延迟信号的输出路径上的多路复用器延迟
公开(公告)号：US09319040B2
公开(公告)日：2016-04-19
申请号：US14580655
申请日：2014-12-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Huu N. Dinh , Robert S. Horton , Bill N. On
IPC分类号： H03L7/00 , H03K5/159 , H03K3/037 , H03K19/173 , H03K5/00
CPC分类号： H03K5/159 , H03K3/037 , H03K19/1737 , H03K2005/00104 , H03K2005/00241
摘要： A controller sets a selector register of programmable delay signal logic is to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory. The controller controls a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal. The controller waits required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.
摘要翻译：控制器将可编程延迟信号逻辑的选择器寄存器设置为等于从集成电路输出到外部存储器的信号所需的延迟时钟周期数。控制器控制沿着输出路径的附加逻辑的选择，以在时钟周期内执行延迟信号，而不会通过输出延迟信号的延迟信号逻辑将任何延迟加到输出路径上。在使用由延迟信号逻辑输出的延迟信号到输出路径之后，控制器在设置选择器寄存器之后等待所需的时钟周期数。

84. 发明授权

US09294114B2 Reference signal generating circuit, ad conversion circuit, and imaging device 有权
标题翻译：参考信号发生电路，广告转换电路和成像装置
公开(公告)号：US09294114B2
公开(公告)日：2016-03-22
申请号：US14090569
申请日：2013-11-26
申请人： OLYMPUS CORPORATION
发明人： Yoshio Hagihara
IPC分类号： H03K3/01 , G01J1/44 , H03M1/34 , H04N5/376 , H04N5/378 , H03M1/56 , H03K5/00
CPC分类号： H03M1/34 , H03K2005/00241 , H03M1/56 , H04N5/3765 , H04N5/378
摘要： A reference signal generating circuit, an AD conversion circuit, and an imaging device are provided. A clock generating unit includes a delay section including delay units, each of which delays an input signal and outputs a delayed signal, and outputs a low-order phase signal based on a signal output from the delay section. A high-order current source cell unit includes high-order current source cells, each of which generates the same constant current. A low-order current source cell unit includes low-order current source cells weighted to generate constant currents having current values that differ by a predetermined proportion of a current value of the constant current generated by the high-order current source cell. Selection of the high-order current source cell is performed based on a clock obtained by dividing a clock based on the low-order phase signal.
摘要翻译：提供了参考信号发生电路，AD转换电路和成像装置。时钟发生单元包括延迟部分，其包括延迟单元，每个延迟单元延迟输入信号并输出延迟信号，并且基于从延迟部分输出的信号输出低阶相位信号。高阶电流源单元单元包括高阶电流源单元，每个单元产生相同的恒定电流。低阶电流源单元单元包括加权的低阶电流源单元，以产生恒定电流，该恒定电流的电流值与由高阶电流源单元产生的恒定电流的当前值的预定比例相差。基于通过基于低阶相位信号划分时钟而获得的时钟来执行高阶电流源单元的选择。

85. 发明申请

US20150102846A1 DISTRIBUTING MULTIPLEXING LOGIC TO REMOVE MULTIPLEXOR LATENCY ON THE OUTPUT PATH FOR VARIABLE CLOCK CYCLE, DELAYED SIGNALS 有权
标题翻译：分配多路复用逻辑，以便在可变时钟周期的输出路径上移除多路复用器延迟信号，延迟信号
公开(公告)号：US20150102846A1
公开(公告)日：2015-04-16
申请号：US14580655
申请日：2014-12-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： HUU N. DINH , ROBERT S. HORTON , BILL N. ON
IPC分类号： H03K5/159 , H03K19/173 , H03K3/037
CPC分类号： H03K5/159 , H03K3/037 , H03K19/1737 , H03K2005/00104 , H03K2005/00241
摘要： A controller sets a selector register of programmable delay signal logic is to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory. The controller controls a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal. The controller waits required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.
摘要翻译：控制器将可编程延迟信号逻辑的选择器寄存器设置为等于从集成电路输出到外部存储器的信号所需的延迟时钟周期数。控制器控制沿着输出路径的附加逻辑的选择，以在时钟周期内执行延迟信号，而不会通过输出延迟信号的延迟信号逻辑将任何延迟加到输出路径上。在使用由延迟信号逻辑输出的延迟信号到输出路径之后，控制器在设置选择器寄存器之后等待所需的时钟周期数。

86. 发明申请

US20140002164A1 DELAY CIRCUIT AND DELAY METHOD USING THE SAME 有权
标题翻译：延迟电路和延迟方法
公开(公告)号：US20140002164A1
公开(公告)日：2014-01-02
申请号：US13716816
申请日：2012-12-17
申请人： SK HYNIX INC.
发明人： Choung-Ki SONG
IPC分类号： H03H11/26
CPC分类号： H03H11/26 , H03K5/133 , H03K2005/00241
摘要： A delay circuit includes a delay unit configured to generate a delayed transmission signal by delaying a transmission signal activated when a first signal or a second signal is activated, a signal type storing unit configured to store whether the first signal and the second signal is activated, and a transmitting unit configured to transmits the delayed transmission signal as a first delayed signal or a second delayed signal in response to a value stored in the signal type storing unit.
摘要翻译：延迟电路包括：延迟单元，被配置为通过延迟在第一信号或第二信号被激活时激活的传输信号来产生延迟的传输信号;信号类型存储单元，被配置为存储第一信号和第二信号是否被激活; 以及发送单元，被配置为响应于存储在信号类型存储单元中的值，将延迟的发送信号作为第一延迟信号或第二延迟信号进行发送。

87. 发明授权

US08427195B1 Digital signal generator and automatic test equipment having the same 有权
标题翻译：数字信号发生器和具有相同功能的自动测试设备
公开(公告)号：US08427195B1
公开(公告)日：2013-04-23
申请号：US13468668
申请日：2012-05-10
申请人： Seong Kwan Lee , Hyun Woo Choi , Sung Yeol Kim , David Keezer , Carl Gray , Te-Hui Chen
发明人： Seong Kwan Lee , Hyun Woo Choi , Sung Yeol Kim , David Keezer , Carl Gray , Te-Hui Chen
IPC分类号： H03K19/00
CPC分类号： H03K19/21 , H03K2005/00241
摘要： A digital signal generator includes an input unit configured to receive signal information of a target data signal, a controller configured to calculate at least two delay values and at least two data values, the at least two delay values and the at least two data values being used to generate a data signal corresponding to the signal information input through the input unit, a multi-phase clock generator configured to delay a reference clock signal based on the at least two delay values to generate at least two clock signals having different phases, a signal generator configured to generate at least two data signals by assigning the at least two data values to the at least two clock signals, and a logic gate unit configured to generate the data signal corresponding to the signal information input through the input unit based on the at least two data signals.
摘要翻译：数字信号发生器包括被配置为接收目标数据信号的信号信息的输入单元，配置成计算至少两个延迟值和至少两个数据值的控制器，所述至少两个延迟值和至少两个数据值是用于产生与通过输入单元输入的信号信息相对应的数据信号;多相时钟发生器，被配置为基于所述至少两个延迟值来延迟参考时钟信号，以产生具有不同相位的至少两个时钟信号; 信号发生器，被配置为通过将至少两个数据值分配给所述至少两个时钟信号来产生至少两个数据信号;以及逻辑门单元，被配置为基于所述至少两个时钟信号生成与通过所述输入单元输入的信号信息相对应的数据信号至少两个数据信号。

88. 发明申请

US20100167678A1 RECEIVER CIRCUIT AND DATA TRANSMISSION SYSTEM 有权
标题翻译：接收电路和数据传输系统
公开(公告)号：US20100167678A1
公开(公告)日：2010-07-01
申请号：US12601433
申请日：2008-02-26
申请人： Takefumi Yoshikawa
发明人： Takefumi Yoshikawa
IPC分类号： H04B1/10 , H04B1/16
CPC分类号： H03K19/018507 , H03K3/356017 , H03K5/06 , H03K5/133 , H03K2005/00058 , H03K2005/00241 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L25/08 , H04L25/493
摘要： A receiver circuit which can suppress a voltage amplitude appearing on a transmission line. The receiver circuit, coupled to a first and a second transmission lines which transmit information by using currents, includes a first and a second current sources, a first and a second conversion sections which convert currents which flow respectively therein to voltages, a first transistor whose source is coupled to the first current source and to the first transmission line, and whose drain is coupled to the first conversion section, and a second transistor whose source is coupled to the second current source and to the second transmission line, and whose drain is coupled to the second conversion section. The gate and the drain of the first transistor are respectively coupled to the drain and the gate of the second transistor.
摘要翻译：一种可以抑制出现在传输线上的电压振幅的接收机电路。耦合到通过使用电流传输信息的第一和第二传输线的接收机电路包括第一和第二电流源，第一和第二转换部分，其将分别流入其中的电流转换成电压;第一晶体管，源极耦合到第一电流源和第一传输线，并且其漏极耦合到第一转换部分，以及第二晶体管，其源极耦合到第二电流源和第二传输线，并且其漏极是耦合到第二转换部分。第一晶体管的栅极和漏极分别耦合到第二晶体管的漏极和栅极。

89. 发明授权

US07496167B2 Storage efficient sliding window sum 失效
标题翻译：存储高效滑窗总和
公开(公告)号：US07496167B2
公开(公告)日：2009-02-24
申请号：US11306986
申请日：2006-01-18
申请人： Cindy Chun Wang , Xiangyang Simon Xu , Xiaochun Chen
发明人： Cindy Chun Wang , Xiangyang Simon Xu , Xiaochun Chen
IPC分类号： H04L7/00
CPC分类号： H04L27/22 , H03K2005/00241 , H04L27/2275 , H04L2025/03401 , H04L2027/0046 , H04L2027/0063
摘要： A delay buffer includes a first shift register receiving input data and having a shift signal input port. The first shift register right shifts the input data responsive to a shift signal on the shift signal input port. The shift signal is determined based on an effective bit width of the input data. A first delay line receives the shifted data from the first shift register while a second delay line of equal length to the first delay line receives the shift signal. A second shift register receives the output from the first delay line and receives the output of the second delay line on a shift signal input port. The second shift register then left shifts the data contained therein according to the shift signal.
摘要翻译：延迟缓冲器包括接收输入数据并具有移位信号输入端口的第一移位寄存器。第一移位寄存器根据移位信号输入端口上的移位信号，右移位输入数据。基于输入数据的有效位宽来确定移位信号。第一延迟线接收来自第一移位寄存器的移位数据，而与第一延迟线等长的第二延迟线接收移位信号。第二移位寄存器接收来自第一延迟线的输出，并接收移位信号输入端口上的第二延迟线的输出。然后，第二移位寄存器根据移位信号移位其中包含的数据。

90. 发明申请

US20090003428A1 Method and apparatus for treating a signal 有权
标题翻译：用于治疗信号的方法和装置
公开(公告)号：US20090003428A1
公开(公告)日：2009-01-01
申请号：US11824410
申请日：2007-06-29
申请人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
发明人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
IPC分类号： H03K7/08
CPC分类号： H03K5/135 , H03K2005/00058 , H03K2005/00234 , H03K2005/00241
摘要： A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.
摘要翻译：一种方法包括：当偏移偏离第一方向的值时，延迟至少一个信号的偏移的第一数量的时钟相位; 以及当所述偏移在所述第二方向上偏离所述值时，将所述至少一个信号的偏移延迟到所述第二数量的时钟相位。时钟相位的第一个数量与第二个时钟相位数不同。所述至少一个信号与在每个相应时钟周期中具有多个时钟相位的呈现后续时钟周期的时钟信号基本同步地影响多个后续偏移。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式