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1. 发明授权

US08580628B2 Integrated circuit contact structure and method 有权
标题翻译：集成电路接触结构及方法
公开(公告)号：US08580628B2
公开(公告)日：2013-11-12
申请号：US13365030
申请日：2012-02-02
申请人： André P. Labonté , Richard S. Wise , Ying Li , Brett H. Engel
发明人： André P. Labonté , Richard S. Wise , Ying Li , Brett H. Engel
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L21/76834 , H01L21/823828 , H01L21/823871 , H01L29/66545
摘要： An integrated circuit having a mis-alignment tolerant electrical contact is formed by providing a semiconductor containing substrate over which is a first FET gate laterally bounded by a first dielectric region, replacing an upper portion of the first FET gate with a second dielectric region, applying a mask having an opening extending partly over an adjacent source or drain contact region of the substrate and over a part of the second dielectric region above the first FET gate, forming an opening through the first dielectric region extending to the contact region and the part of the second dielectric region, and filling the opening with a conductor making electrical connection with the contact region but electrically insulated from the first FET gate by the second dielectric region. A further FET gate may also be provided having an electrical contact thereto formed separately from the source-drain contact.
摘要翻译：具有不对准容限的电接触的集成电路是通过提供半导体衬底形成的，其上是由第一介电区横向界定的第一FET栅极，用第二电介质区域代替第一FET栅极的上部，施加掩模，其具有部分地在所述衬底的相邻源极或漏极接触区域上方延伸的开口以及在所述第一FET栅极上方的所述第二电介质区域的一部分上方，形成穿过延伸到所述接触区域的所述第一电介质区域的开口，第二电介质区域，并且用与该接触区域电连接但与第一FET栅极与第二电介质区域电绝缘的导体填充该开口。还可以提供另外的FET栅极，其具有与源极 - 漏极触点分开形成的电接触。

2. 发明申请

US20130001786A1 OVERLAPPING CONTACTS FOR SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的重叠接触
公开(公告)号：US20130001786A1
公开(公告)日：2013-01-03
申请号：US13171657
申请日：2011-06-29
申请人： Brett H. Engel , Lindsey Hall , David F. Hilscher , Randolph F. Knarr , Steven R. Soss , Jin Z. Wallner
发明人： Brett H. Engel , Lindsey Hall , David F. Hilscher , Randolph F. Knarr , Steven R. Soss , Jin Z. Wallner
IPC分类号： H01L21/28 , H01L23/48
CPC分类号： H01L23/528 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.
摘要翻译：在半导体器件中形成重叠触点的方法包括在电介质层中形成第一触点; 蚀刻电介质层以形成与第一接触相邻的凹部，并且在蚀刻介电层的同时去除第一接触的顶部，其中在电介质层中形成凹部之后第一接触的底部保留在电介质层中 ; 以及在与所述第一接触件的底部相邻的所述凹部中形成第二触点，并且在所述第一接触件的底部的顶表面的顶部上形成第二接触。

3. 发明授权

US06914320B2 Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof 有权
标题翻译：双层HDP CVD / PE CVD帽在先进的BEOL互连结构及其方法
公开(公告)号：US06914320B2
公开(公告)日：2005-07-05
申请号：US10807029
申请日：2004-03-23
申请人： Tze-Chiang Chen , Brett H. Engel , John A. Fitzsimmons , Terence Kane , Naftall E. Lustig , Ann McDonald , Vincent McGahay , Soon-Cheon Seo , Anthony K. Stamper , Yun Yu Wang , Erdem Kaltalioglu
发明人： Tze-Chiang Chen , Brett H. Engel , John A. Fitzsimmons , Terence Kane , Naftall E. Lustig , Ann McDonald , Vincent McGahay , Soon-Cheon Seo , Anthony K. Stamper , Yun Yu Wang , Erdem Kaltalioglu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.
摘要翻译：公开了一种先进的后端（BEOL）金属化结构。该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由介电材料形成，优选沉积通过等离子体增强化学气相沉积（PE CVD）工艺。还公开了一种用于形成BEOL金属化结构的方法。本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

4. 发明申请

US20120306093A1 CONVERTING METAL MASK TO METAL-OXIDE ETCH STOP LAYER AND RELATED SEMICONDUCTOR STRUCTURE 有权
标题翻译：将金属掩模转换为金属氧化物蚀刻停止层和相关半导体结构
公开(公告)号：US20120306093A1
公开(公告)日：2012-12-06
申请号：US13151646
申请日：2011-06-02
申请人： Brett H. Engel , Ying Li , Viraj Y. Sardesai , Richard S. Wise
发明人： Brett H. Engel , Ying Li , Viraj Y. Sardesai , Richard S. Wise
IPC分类号： H01L21/283 , H01L23/48 , B82Y40/00 , B82Y99/00
CPC分类号： H01L21/31144 , H01L21/02178 , H01L21/02244 , H01L21/02252 , H01L21/76804 , H01L21/7681 , H01L21/76829
摘要： A method includes providing a semiconductor structure including a plurality of devices; depositing a nitride cap over the semiconductor structure; forming an aluminum mask over the nitride cap, the aluminum mask including a plurality of first openings; converting the aluminum mask to an aluminum oxide etch stop layer; and performing middle-of-line fabrication processing, leaving the aluminum oxide etch stop layer in place. A semiconductor structure includes a plurality of devices on a substrate; a nitride cap over the plurality of devices; an aluminum oxide etch stop layer over the nitride cap; an inter-level dielectric (ILD) over the aluminum oxide etch stop layer; and a plurality of contacts extending through the ILD, the aluminum oxide etch stop layer and the nitride cap to the plurality of devices.
摘要翻译：一种方法包括提供包括多个装置的半导体结构; 在所述半导体结构上沉积氮化物盖; 在所述氮化物盖上形成铝掩模，所述铝掩模包括多个第一开口; 将铝掩模转变成氧化铝蚀刻停止层; 并执行中间线制造处理，将氧化铝蚀刻停止层留在原位。半导体结构在基板上包括多个器件; 多个装置上的氮化物盖; 在氮化物盖上方的氧化铝蚀刻停止层; 氧化铝蚀刻停止层上的层间电介质（ILD）; 以及穿过ILD延伸的多个触点，氧化铝蚀刻停止层和氮化物帽到多个器件。

5. 发明授权

US07163883B2 Edge seal for a semiconductor device 有权
标题翻译：半导体器件的边缘密封
公开(公告)号：US07163883B2
公开(公告)日：2007-01-16
申请号：US10694500
申请日：2003-10-27
申请人： Birendra N. Agarwala , Hormazdyar Minocher Dalal , Eric G. Liniger , Diana Llera-Hurlburt , Du Binh Nguyen , Richard W. Procter , Hazara Singh Rathore , Chunyan E. Tian , Brett H. Engel
发明人： Birendra N. Agarwala , Hormazdyar Minocher Dalal , Eric G. Liniger , Diana Llera-Hurlburt , Du Binh Nguyen , Richard W. Procter , Hazara Singh Rathore , Chunyan E. Tian , Brett H. Engel
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/8238
CPC分类号： H01L21/76831 , H01L21/76801 , H01L21/76807
摘要： An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.
摘要翻译：围绕集成电路器件周边的边缘密封，其环境地保护铜电路免受在切割期间可能在低k层间电介质中形成的裂纹。边缘密封件基本上构成在集成电路器件周边附近的铜电路和低k层间电介质之间的电介质壁。电介质壁是与低k层间电介质不同的材料。

6. 发明授权

US07008803B2 Method of reworking structures incorporating low-k dielectric materials 失效
标题翻译：包含低k电介质材料的返修结构的方法
公开(公告)号：US07008803B2
公开(公告)日：2006-03-07
申请号：US10280513
申请日：2002-10-24
申请人： Terence Lawrence Kane , Chung-Ping Eng , Brett H. Engel , Barry Jack Ginsberg , Dermott A. Macpherson , John Charles Petrus
发明人： Terence Lawrence Kane , Chung-Ping Eng , Brett H. Engel , Barry Jack Ginsberg , Dermott A. Macpherson , John Charles Petrus
IPC分类号： H01L21/00
CPC分类号： H01L21/67253 , G01N21/68 , H01J37/32009 , H01L21/31111 , H01L21/31116 , H01L21/31127 , H01L21/31138 , H01L21/32131 , H01L2924/0002 , H01L2924/00
摘要： Methods of etching a semiconductor structure using ion milling with a variable-position endpoint detector to unlayer multiple interconnect layers, including low-k dielectric films. The ion milling process is controlled for each material type to maintain a planar surface with minimal damage to the exposed materials. In so doing, an ion beam mills a first layer and detects an endpoint thereof using an optical detector positioned within the ion beam adjacent the first layer to expose a second layer of low-k dielectric film. Once the low-k dielectric film is exposed, a portion of the low-k dielectric film may be removed to provide spaces therein, which are backfilled with a material and polished to remove the backfill material and a layer of the multiple interconnect metal layers. Still further, the exposed low-k dielectric film may then be removed, and the exposed metal vias polished.
摘要翻译：使用可变位置端点检测器使用离子铣削蚀刻半导体结构以使多层互连层（包括低k介电膜）层叠的方法。对于每种材料类型来控制离子研磨工艺以保持平坦表面，同时对暴露的材料具有最小的损伤。这样做，离子束研磨第一层并使用位于邻近第一层的离子束内的光学检测器来检测其端点，以暴露第二层低k电介质膜。一旦露出低k电介质膜，可以去除低k电介质膜的一部分以在其中提供空间，其中填充有材料并被抛光以去除回填材料和多个互连金属层的层。此外，然后可以去除暴露的低k电介质膜，并且暴露的金属通孔被抛光。

7. 发明授权

US06887783B2 Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof 有权
标题翻译：双层HDP CVD / PE CVD帽预先BEOL互连结构及其方法
公开(公告)号：US06887783B2
公开(公告)日：2005-05-03
申请号：US10650890
申请日：2003-08-28
申请人： Tze-Chiang Chen , Brett H. Engel , John A. Fitzsimmons , Terence Kane , Naftall E. Lustig , Ann McDonald , Vincent McGahay , Soon-Cheon Seo , Anthony K. Stamper , Yun Yu Wang , Erdem Kaltalioglu
发明人： Tze-Chiang Chen , Brett H. Engel , John A. Fitzsimmons , Terence Kane , Naftall E. Lustig , Ann McDonald , Vincent McGahay , Soon-Cheon Seo , Anthony K. Stamper , Yun Yu Wang , Erdem Kaltalioglu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.
摘要翻译：公开了一种先进的后端（BEOL）金属化结构。该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由介电材料形成，优选沉积通过等离子体增强化学气相沉积（PE CVD）工艺。还公开了一种用于形成BEOL金属化结构的方法。本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

8. 发明授权

US08435891B2 Converting metal mask to metal-oxide etch stop layer and related semiconductor structure 有权
标题翻译：将金属掩模转换为金属氧化物蚀刻停止层和相关的半导体结构
公开(公告)号：US08435891B2
公开(公告)日：2013-05-07
申请号：US13151646
申请日：2011-06-02
申请人： Brett H. Engel , Ying Li , Viraj Y. Sardesai , Richard S. Wise
发明人： Brett H. Engel , Ying Li , Viraj Y. Sardesai , Richard S. Wise
IPC分类号： H01L21/283
CPC分类号： H01L21/31144 , H01L21/02178 , H01L21/02244 , H01L21/02252 , H01L21/76804 , H01L21/7681 , H01L21/76829
摘要： A method includes providing a semiconductor structure including a plurality of devices; depositing a nitride cap over the semiconductor structure; forming an aluminum mask over the nitride cap, the aluminum mask including a plurality of first openings; converting the aluminum mask to an aluminum oxide etch stop layer; and performing middle-of-line fabrication processing, leaving the aluminum oxide etch stop layer in place. A semiconductor structure includes a plurality of devices on a substrate; a nitride cap over the plurality of devices; an aluminum oxide etch stop layer over the nitride cap; an inter-level dielectric (ILD) over the aluminum oxide etch stop layer; and a plurality of contacts extending through the ILD, the aluminum oxide etch stop layer and the nitride cap to the plurality of devices.
摘要翻译：一种方法包括提供包括多个装置的半导体结构; 在所述半导体结构上沉积氮化物盖; 在所述氮化物盖上形成铝掩模，所述铝掩模包括多个第一开口; 将铝掩模转变成氧化铝蚀刻停止层; 并执行中间线制造处理，将氧化铝蚀刻停止层留在原位。半导体结构在基板上包括多个器件; 多个装置上的氮化物盖; 在氮化物盖上方的氧化铝蚀刻停止层; 氧化铝蚀刻停止层上的层间电介质（ILD）; 以及穿过ILD延伸的多个触点，氧化铝蚀刻停止层和氮化物帽到多个器件。

9. 发明授权

US07098676B2 Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor 失效
标题翻译：多功能结构，用于增强低k电介质半导体的芯片制造和可靠性，以及裂纹完整性屏幕和监视器
公开(公告)号：US07098676B2
公开(公告)日：2006-08-29
申请号：US10338931
申请日：2003-01-08
申请人： William F. Landers , Thomas M. Shaw , Diana Llera-Hurlburt , Scott W. Crowder , Vincent J. McGahay , Sandra G. Malhotra , Charles R. Davis , Ronald D. Goldblatt , Brett H. Engel
发明人： William F. Landers , Thomas M. Shaw , Diana Llera-Hurlburt , Scott W. Crowder , Vincent J. McGahay , Sandra G. Malhotra , Charles R. Davis , Ronald D. Goldblatt , Brett H. Engel
IPC分类号： G01R27/08 , G01R31/26 , H01L31/07 , H01L23/58
CPC分类号： H01L23/585 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.
摘要翻译：片上冗余裂纹终止阻挡结构或裂缝挡板为防止缺陷，裂纹，脱层和水分/氧化污染物到达有源电路区域提供了屏障。阻挡结构设计中的导电材料允许将屏障布线到接触垫和器件引脚上，用于将监测器件耦合到芯片以监测屏障完整性。

10. 发明授权

US06478212B1 Bond pad structure and method for reduced downward force wirebonding 有权
标题翻译：焊盘结构和减小向下力线接合的方法
公开(公告)号：US06478212B1
公开(公告)日：2002-11-12
申请号：US09760955
申请日：2001-01-16
申请人： Brett H. Engel , Vincent James McGahay , Henry Atkinson Nye, III
发明人： Brett H. Engel , Vincent James McGahay , Henry Atkinson Nye, III
IPC分类号： B23K3700
CPC分类号： H01L24/85 , B23K20/007 , B23K33/00 , H01L24/03 , H01L24/05 , H01L24/46 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05552 , H01L2224/05557 , H01L2224/05571 , H01L2224/05624 , H01L2224/4807 , H01L2224/4809 , H01L2224/48463 , H01L2224/49111 , H01L2224/85205 , H01L2224/85214 , H01L2224/85365 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/04953 , H01L2924/14 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A bond pad structure for an integrated circuit has bondable base member for receiving a wire bonded thereon. A cavity is formed within the base member, with the cavity being configured to capture the wire therein. The cavity has one end having a first width and an opposite end having a second width, with the first width being greater than second width.
摘要翻译：用于集成电路的接合焊盘结构具有用于接收其上键合的引线的可粘合的基底构件。空腔形成在基座构件内，空腔构造成在其中捕获线。空腔具有第一宽度的一端和具有第二宽度的相对端，第一宽度大于第二宽度。

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