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1. 发明授权

US09244846B2 Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses 有权
标题翻译：确保交易存储访问的因果关系与非事务性存储访问进行交互
公开(公告)号：US09244846B2
公开(公告)日：2016-01-26
申请号：US13543325
申请日：2012-07-06
申请人： Bradly G. Frey , Cathy May , Derek E. Williams
发明人： Bradly G. Frey , Cathy May , Derek E. Williams
IPC分类号： G06F12/08 , G06F9/46
CPC分类号： G06F12/0842 , G06F9/466 , G06F12/0813 , G06F12/0831
摘要： A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction.
摘要翻译：数据处理系统为分布式共享存储器系统实现弱一致性存储器模型。数据处理系统在多个处理器核心上同时执行存储器事务内的一个或多个事务存储器指令和一个或多个非事务存储器指令。一个或多个非事务存储器指令包括非事务存储指令。数据处理系统只是为了响应于关于存储器事务的非事务性存储指令的因果关系的强制而将存储器事务提交给分布式共享存储器系统。

2. 发明申请

US20140040557A1 NESTED REWIND ONLY AND NON REWIND ONLY TRANSACTIONS IN A DATA PROCESSING SYSTEM SUPPORTING TRANSACTIONAL STORAGE ACCESSES 有权
标题翻译：仅在数据处理系统中仅限于仅限于和非重新开发的交易，支持交易存储访问
公开(公告)号：US20140040557A1
公开(公告)日：2014-02-06
申请号：US13650448
申请日：2012-10-12
申请人： BRADLY G. FREY , GUY L. GUTHRIE , CATHY MAY , DEREK E. WILLIAMS
发明人： BRADLY G. FREY , GUY L. GUTHRIE , CATHY MAY , DEREK E. WILLIAMS
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F9/467 , G06F12/0815
摘要： In a multiprocessor data processing system having a distributed shared memory system, first and second nested memory transactions are executed, where the first memory transaction is a rewind-only transaction (ROT) and the second memory transaction is a non-ROT memory transaction. The first memory transaction has a transaction body including the second memory transaction and an additional plurality of transactional memory access instructions. In response to execution of the transactional memory access instructions, memory accesses are performed to the distributed shared memory system. Conflicts between memory accesses not within the first memory transaction and at least a load footprint of any of the transactional memory access instructions preceding the second memory transaction are not tracked. However, conflicts between memory accesses not within the first memory transaction and store and load footprints of any of the transactional memory access instructions that follow initiation the second memory transaction are tracked.
摘要翻译：在具有分布式共享存储器系统的多处理器数据处理系统中，执行第一和第二嵌套存储器事务，其中第一存储器事务是倒退事务（ROT），而第二存储器事务是非ROT存储器事务。第一存储器事务具有包括第二存储器事务和附加的多个事务存储器访问指令的事务主体。响应于事务存储器访问指令的执行，对分布式共享存储器系统执行存储器访问。不在第一存储器事务内的存储器访问与至少在第二存储器事务之前的任何事务存储器访问指令的负载覆盖区之间的冲突不被跟踪。然而，跟踪不在第一存储器事务内的存储器访问之间的冲突，并且跟踪启动第二存储器事务之后的任何事务存储器访问指令的存储和负载占用。

3. 发明申请

US20140013055A1 ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES 审中-公开
标题翻译：确保与非交易存储访问交互的交易存储访问的原理
公开(公告)号：US20140013055A1
公开(公告)日：2014-01-09
申请号：US13777161
申请日：2013-02-26
申请人： Bradly G. Frey , Cathy May , Derek E. Williams
发明人： Bradly G. Frey , Cathy May , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F9/466 , G06F12/0813 , G06F12/0831
摘要： A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction.
摘要翻译：数据处理系统为分布式共享存储器系统实现弱一致性存储器模型。数据处理系统在多个处理器核心上同时执行存储器事务内的一个或多个事务存储器指令和一个或多个非事务存储器指令。一个或多个非事务存储器指令包括非事务存储指令。数据处理系统只是为了响应于关于存储器事务的非事务性存储指令的因果关系的强制而将存储器事务提交给分布式共享存储器系统。

4. 发明申请

US20120246658A1 Transactional Memory Preemption Mechanism 失效
公开(公告)号：US20120246658A1
公开(公告)日：2012-09-27
申请号：US13465115
申请日：2012-05-07
申请人： Richard L. Arndt , Harold W. Cain, III , Bradly G. Frey , Cathy May
发明人： Richard L. Arndt , Harold W. Cain, III , Bradly G. Frey , Cathy May
IPC分类号： G06F9/46
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863
摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

5. 发明申请

US20120084477A1 Transactional Memory Preemption Mechanism 失效
标题翻译：事务记忆抢占机制
公开(公告)号：US20120084477A1
公开(公告)日：2012-04-05
申请号：US12894308
申请日：2010-09-30
申请人： Richard L. Arndt , Harold W. Cain, III , Bradly G. Frey , Cathy May
发明人： Richard L. Arndt , Harold W. Cain, III , Bradly G. Frey , Cathy May
IPC分类号： G06F13/24
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863
摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.
摘要翻译：提供了在数据处理系统中执行事务的机制。在处理器的内部寄存器中生成事务检查点数据结构。事务检查点数据结构存储表示执行相应事务之前的时间的程序寄存器的状态的事务检查点数据。执行包括由处理器执行的代码的第一部分的事务。在执行事务时接收事务的中断，结果，事务检查点数据被存储到数据处理系统的存储器中的数据结构。然后执行第二部分代码。响应于发生的事件导致处理器的执行切换返回到事务的执行，使用数据处理系统的存储器中的数据结构恢复程序寄存器的状态。

6. 发明申请

US20100268885A1 SPECIFYING AN ACCESS HINT FOR PREFETCHING LIMITED USE DATA IN A CACHE HIERARCHY 失效
标题翻译：指定访问提示用于缓存缓存中的有限使用数据
公开(公告)号：US20100268885A1
公开(公告)日：2010-10-21
申请号：US12424681
申请日：2009-04-16
申请人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Balaram Sinharoy , Peter K. Szwed
发明人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Balaram Sinharoy , Peter K. Szwed
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching limited use data. A processing unit receives a data cache block touch (DCBT) instruction having an access hint indicating to the processing unit that a program executing on the data processing system may soon access a cache block addressed within the DCBT instruction. The access hint is contained in a code point stored in a subfield of the DCBT instruction. In response to detecting that the code point is set to a specific value, the data addressed in the DCBT instruction is prefetched into an entry in the lower level cache. The entry may then be updated as a least recently used entry of a plurality of entries in the lower level cache. In response to a new cache block being fetched to the cache, the prefetched cache block is cast out of the cache.
摘要翻译：一种用于指定预取有限使用数据的访问提示的系统和方法。处理单元接收具有指示给处理单元的访问提示的数据高速缓存块触摸（DCBT）指令，即在数据处理系统上执行的程序可以很快访问在DCBT指令内寻址的高速缓存块。访问提示包含在存储在DCBT指令的子字段中的代码点中。响应于检测到代码点被设置为特定值，DCBT指令中寻址的数据被预取到低级缓存中的条目中。然后可以将条目作为较低级别高速缓存中的多个条目的最近最少使用的条目来更新。响应于将新的高速缓存块提取到高速缓存，预取的高速缓存块被抛出高速缓存。

7. 发明申请

US20080034193A1 System and Method for Providing a Mediated External Exception Extension for a Microprocessor 审中-公开
标题翻译：为微处理器提供介入的外部异常扩展的系统和方法
公开(公告)号：US20080034193A1
公开(公告)日：2008-02-07
申请号：US11462601
申请日：2006-08-04
申请人： Michael N. Day , Jonathan J. DeMent , Charles R. Johns , Orran Y. Krieger , Cathy May
发明人： Michael N. Day , Jonathan J. DeMent , Charles R. Johns , Orran Y. Krieger , Cathy May
IPC分类号： G06F7/38
CPC分类号： G06F13/24 , G06F9/32 , G06F9/4812 , G06F2209/481
摘要： A system and method for providing a mediated external exception extension for a microprocessor are provided. With the system and method, in response to an external exception, a hypervisor determines if the associated external interrupt is directed to a logical partition (LPAR) that has external interrupt handling enabled. If so, the hypervisor sets appropriate state restore registers (SRRs) and passes control to an external interrupt handler of the LPAR. If external interrupt handling is not currently enabled by the LPAR, the hypervisor sets a mediated exception request and returns control to the LPAR. Once the operating system of the logical partition re-enables external interrupt handling, a mediated external interrupt occurs, state information for the LPAR is set in the SRRs, and the external interrupt handler of the LPAR is invoked. In this way, external interrupts may be received by the hypervisor even when external interrupt handling is disabled.
摘要翻译：提供了一种用于为微处理器提供介导的外部异常扩展的系统和方法。利用系统和方法，响应于外部异常，管理程序确定相关联的外部中断是否被引导到启用了外部中断处理的逻辑分区（LPAR）。如果是这样，管理程序设置适当的状态恢复寄存器（SRR），并将控制权传递给LPAR的外部中断处理程序。如果LPAR当前未启用外部中断处理，管理程序将设置介入的异常请求并将控制权返回给LPAR。一旦逻辑分区的操作系统重新启用外部中断处理，就会发生中介的外部中断，LPAR的状态信息设置在SRR中，并且调用LPAR的外部中断处理程序。以这种方式，即使禁用外部中断处理，管理程序也可以接收外部中断。

8. 发明授权

US09619345B2 Apparatus for determining failure context in hardware transactional memories 有权
公开(公告)号：US09619345B2
公开(公告)日：2017-04-11
申请号：US13615241
申请日：2012-09-13
申请人： Harold W Cain , Bradly G Frey , Hung Q Le , Cathy May
发明人： Harold W Cain , Bradly G Frey , Hung Q Le , Cathy May
IPC分类号： G06F11/14 , G06F11/07 , G06F9/46
CPC分类号： G06F11/1474 , G06F9/466 , G06F9/467 , G06F11/073 , G06F11/0778
摘要： A processor core includes a transactional memory that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at least one register of the processor core. The processor core stores the context summary information of aborted transactions into the transactional memory or the transaction diagnostic register. The context summary information can be used for diagnosing the aborted transactions.

9. 发明授权

US09268598B2 Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories 有权
标题翻译：记录和分析交易失败源地址和对应于硬件事务存储器中止事务的地址的有效性指示符
公开(公告)号：US09268598B2
公开(公告)日：2016-02-23
申请号：US13615416
申请日：2012-09-13
申请人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
发明人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
IPC分类号： G06F9/46 , G06F11/14 , G06F11/36
CPC分类号： G06F9/467 , G06F11/1474 , G06F11/36 , G06F11/3648
摘要： A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.
摘要翻译：处理器核心包括事务存储器，事务失败指令地址寄存器（TFIAR）和事务故障数据地址寄存器（TFDAR）。事务存储器存储由处理器核心执行的多个事务的信息。处理器核心分别从TFIAR和TFDAR检索与中止事务相关联的指令和数据地址，并将它们存储到一个概要分析表中。然后，处理器核心基于与中止事务相关联的指令和数据地址生成分析信息。

10. 发明申请

US20140047205A1 INTERACTION OF TRANSACTIONAL STORAGE ACCESSES WITH OTHER ATOMIC SEMANTICS 有权
标题翻译：与其他原子语言交互存储访问
公开(公告)号：US20140047205A1
公开(公告)日：2014-02-13
申请号：US13650521
申请日：2012-10-12
申请人： BRADLY G. FREY , GUY L. GUTHRIE , CATHY MAY , DEREK E. WILLIAMS
发明人： BRADLY G. FREY , GUY L. GUTHRIE , CATHY MAY , DEREK E. WILLIAMS
IPC分类号： G06F12/14
CPC分类号： G06F3/0668 , G06F9/467 , G06F12/0811
摘要： In a processor, an instruction sequence including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block is detected. In response to detecting the instruction sequence, the processor causes the conditional write access to the target memory block to fail.
摘要翻译：在处理器中，指令序列依次包括指定对目标存储器块的读取访问的加载和备用指令，属于存储器事务的定界事务存储器存取指令的指令以及指定存储器条件指令的存储条件指令检测到对目标存储器块的条件写访问。响应于检测到指令序列，处理器使对目标存储器块的条件写访问失败。

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