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1. 发明授权

US06691876B2 Semiconductor wafer cassette 有权
标题翻译：半导体晶片盒
公开(公告)号：US06691876B2
公开(公告)日：2004-02-17
申请号：US10056357
申请日：2002-01-25
申请人： Yu-Pin Tsai , Chih-Min Pao , Ching-Feng Tseng , Fu-Tang Chu
发明人： Yu-Pin Tsai , Chih-Min Pao , Ching-Feng Tseng , Fu-Tang Chu
IPC分类号： A47G1908
CPC分类号： H01L21/6732 , H01L21/67326
摘要： A semiconductor wafer cassette has a first side wall, a second side wall opposite the first side wall, a front surface, and a back surface opposite the front surface. A body defines an internal bay portion with slots for vertically receiving wafers, each slot of the internal bay portion having one support slab. The body also includes two parallel legs for supporting the cassette and a handle for handling the cassette.
摘要翻译：半导体晶片盒具有第一侧壁，与第一侧壁相对的第二侧壁，前表面和与前表面相对的后表面。主体限定具有用于垂直接收晶片的槽的内部间隔部分，内部间隔部分的每个槽具有一个支撑板。该主体还包括用于支撑盒的两个平行腿和用于处理盒的手柄。

2. 发明授权

US06503776B2 Method for fabricating stacked chip package 有权
公开(公告)号：US06503776B2
公开(公告)日：2003-01-07
申请号：US09754293
申请日：2001-01-05
申请人： Tsung-Ming Pai , Chih Min Pao , Kuang-Hui Chen
发明人： Tsung-Ming Pai , Chih Min Pao , Kuang-Hui Chen
IPC分类号： H01L2144
CPC分类号： H01L24/32 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/92247 , H01L2225/0651 , H01L2225/06575 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/01087 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要： A method for fabricating a stacked chip package comprises the steps of: (a) attaching a lower chip to a substrate or a lead frame; (b) electrically coupling the lower chip to the substrate or the lead frame; (c) providing a dummy chip with a film adhesive on a upper surface thereof; (d) attaching the dummy chip to the lower chip through an adhesive layer wherein a lower surface of the dummy chip is in contact with the adhesive layer; (e) attaching an upper chip to the dummy chip through the film adhesive; (f) electrically coupling the upper chip to the substrate or the lead frame; and (g) encapsulating the lower chip and the upper chip against a portion of the substrate or the lead frame with a molding compound. Since the dummy chip is bonded to the upper chip via a film adhesive, it is not necessary to monitor the thickness of the film adhesive after the upper chip is bonded to the dummy chip.

3. 发明授权

US06967403B2 Package structure with a heat spreader and manufacturing method thereof 有权
标题翻译：散热器的包装结构及其制造方法
公开(公告)号：US06967403B2
公开(公告)日：2005-11-22
申请号：US10872190
申请日：2004-06-18
申请人： Chi-Ta Chuang , Chih-Min Pao , Chien Liu , Chi-Hao Chiu
发明人： Chi-Ta Chuang , Chih-Min Pao , Chien Liu , Chi-Hao Chiu
IPC分类号： H01L23/36 , H01L23/552 , H01L23/34
CPC分类号： H01L23/552 , H01L23/36 , H01L2224/16225 , H01L2224/73253 , H01L2924/00014 , H01L2924/15311 , H01L2924/16152 , H01L2924/166 , H01L2924/3025 , H01L2224/0401
摘要： A package structure with a heat spreader and manufacturing method thereof is disclosed. The package structure includes a substrate, a ground pad, a heat spreader, a non-conductive adhesive layer, and a pre-solder layer. A die is seated on the substrate, and the ground pad is disposed on the surface of the substrate. The manufacturing method of the package structure includes the following steps: (a) providing the substrate; (b) forming the pre-solder layer on the ground pad by solder paste printing; (c) forming the non-conductive adhesive layer on the substrate surface for being adjacent to the pre-solder layer by adhesive dispensing; (d) disposing the heat spreader onto the non-conductive layer and the pre-solder layer; and (e) heating the non-conductive adhesive layer for solidification and continuing to heat the pre-solder layer for solder reflow so that the heat spreader is adhered to the substrate via the non-conductive adhesive layer and coupled to the ground pad via the pre-solder layer.
摘要翻译：公开了具有散热器的封装结构及其制造方法。封装结构包括衬底，接地垫，散热器，非导电粘合剂层和预焊料层。模具坐在基板上，接地垫设置在基板的表面上。封装结构的制造方法包括以下步骤：（a）提供衬底; （b）通过焊膏印刷在接地焊盘上形成预焊料层; （c）通过粘合剂分配在所述基板表面上形成与所述预焊料层相邻的所述非导电粘合剂层; （d）将散热器设置在非导电层和预焊料层上; 和（e）加热不导电粘合剂层以进行固化，并继续加热用于焊料回流的预焊料层，使得散热器经由非导电粘合剂层粘合到基板上，并经由预焊层。

4. 发明申请

US20090079045A1 Package structure and manufacturing method thereof 审中-公开
标题翻译：包装结构及其制造方法
公开(公告)号：US20090079045A1
公开(公告)日：2009-03-26
申请号：US12232410
申请日：2008-09-17
申请人： Chih-Min Pao
发明人： Chih-Min Pao
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L23/49551 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/16245 , H01L2924/00014 , H01L2924/01079 , H01L2224/05599
摘要： A quad-flat non-leaded (QFN) multichip package and a multichip package are provided. The QFN multichip package includes a lead frame, a first chip, a second chip and a molding compound. The lead frame has a plurality of first leads and second leads alternately arranged with each other. Each first lead includes a first connection portion and a first contact portion. Each second lead includes a second connection portion, a bending part and a second contact portion. The bending part is bent upward such that an interval is formed between the second contact portion and the first contact portion. The first chip is disposed between the first leads and the second leads. The second chip is disposed above the first chip. The molding compound encloses the first chip, the second chip, the first leads and the second leads, and further exposes the lower surfaces of the first and the second leads.
摘要翻译：提供四平面非引脚（QFN）多芯片封装和多芯片封装。 QFN多芯片封装包括引线框架，第一芯片，第二芯片和模塑料。引线框架具有彼此交替布置的多个第一引线和第二引线。每个第一引线包括第一连接部分和第一接触部分。每个第二引线包括第二连接部分，弯曲部分和第二接触部分。弯曲部分向上弯曲，使得在第二接触部分和第一接触部分之间形成间隔。第一芯片设置在第一引线和第二引线之间。第二芯片设置在第一芯片上方。成型复合体包围第一芯片，第二芯片，第一引线和第二引线，并进一步暴露第一引线和第二引线的下表面。

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