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1. 发明授权

US08785790B2 High strength through-substrate vias 有权
标题翻译：高强度通衬底通孔
公开(公告)号：US08785790B2
公开(公告)日：2014-07-22
申请号：US13293698
申请日：2011-11-10
申请人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Belgacem Haba , Hiroaki Sato , Philip Damberg
发明人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Belgacem Haba , Hiroaki Sato , Philip Damberg
IPC分类号： H05K1/11 , H01K3/10
CPC分类号： H05K1/115 , H01L23/14 , H01L23/49827 , H01L23/49866 , H01L2924/0002 , H05K1/03 , H05K1/09 , H05K3/42 , H05K2201/0141 , H05K2201/0175 , H05K2201/09509 , H05K2201/10378 , H05K2203/025 , H05K2203/1105 , Y10T29/49165 , H01L2924/00
摘要： A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.
摘要翻译：组件包括具有第一和第二间隔开并平行表面的支撑结构以及沿第一和第二表面之间的方向延伸的多个导电元件。每个导电元件包含选自铜，铝，镍和铬的布线金属的合金和选自由镓，锗，铟，硒，锡，硫，银，磷和铋。该合金具有随导电元件的至少一个方向上的距离而变化的组成。添加剂的浓度小于或等于导电元件的总原子质量的5％，并且导电元件的电阻率在2.5至30微欧姆厘米之间。

2. 发明授权

US07309406B2 Method and apparatus for plating and polishing semiconductor substrate 有权
标题翻译：电镀和抛光半导体衬底的方法和装置
公开(公告)号：US07309406B2
公开(公告)日：2007-12-18
申请号：US10946703
申请日：2004-09-21
申请人： Homayoun Talieh , Cyprian Emeka Uzoh
发明人： Homayoun Talieh , Cyprian Emeka Uzoh
IPC分类号： C25F3/30
CPC分类号： B24B37/16 , C25D5/06 , C25D5/22 , C25D7/123 , C25D17/001 , C25D17/14 , C25F7/00 , H01L21/3212
摘要： The present invention provides a method and apparatus that plates/deposits a conductive material on a semiconductor substrate and then polishes the same substrate. This is achieved by providing multiple chambers in a single apparatus, where one chamber can be used for plating/depositing the conductive material and another chamber can be used for polishing the semiconductor substrate. The plating/depositing process can be performed using brush plating or electro chemical mechanical deposition and the polishing process can be performed using electropolishing or chemical mechanical polishing. The present invention further provides a method and apparatus for intermittently applying the conductive material to the semiconductor substrate and also intermittently polishing the substrate when such conductive material is not being applied to the substrate. Furthermore, the present invention provides a method and apparatus that plates/deposits and/or polishes a conductive material and improves the electrolyte mass transfer properties on a substrate using a novel anode assembly.
摘要翻译：本发明提供一种在半导体衬底上沉积/沉积导电材料然后抛光相同衬底的方法和装置。这通过在单个设备中提供多个室来实现，其中一个室可以用于电镀/沉积导电材料，并且另一个室可以用于抛光半导体衬底。电镀/沉积工艺可以使用刷镀或电化学机械沉积进行，并且可以使用电抛光或化学机械抛光进行抛光工艺。本发明还提供了一种用于将导电材料间歇地施加到半导体衬底的方法和装置，并且当这种导电材料未被施加到衬底时也间歇地抛光衬底。此外，本发明提供了一种使用新型阳极组件对导电材料进行平板/沉积和/或抛光并改善基板上的电解质传质性质的方法和装置。

3. 发明授权

US06630059B1 Workpeice proximity plating apparatus 失效
标题翻译：工件接近电镀设备
公开(公告)号：US06630059B1
公开(公告)日：2003-10-07
申请号：US09483095
申请日：2000-01-14
申请人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol , Douglas W. Young
发明人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol , Douglas W. Young
IPC分类号： C25D1700
CPC分类号： B24B37/20 , B24B37/046 , B24B37/24 , B24B37/26 , C25D5/06 , C25D17/001 , C25D17/14 , C25F7/00 , H01L21/2885 , H01L21/76877
摘要： The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece. Upon application of power to the anode plate and the cathode workpiece, the electrolyte solution disposed in the plating apparatus is used to deposit the conductive material on the workpiece surface using cylindrical rollers having the pad or blade type objects.
摘要翻译：本发明涉及通过旋转靠近基板的垫片或刀片型物体来在半导体衬底上镀覆导电材料的方法和装置，从而消除/减少凹陷和空隙。这通过提供安装在圆柱形阳极或辊子上的垫片或刀片型物体，并使用设置在垫片上或穿过垫片上的电解质溶液将导电材料施加到衬底来实现。在本发明的一个实施例中，衬垫或刀片型物体安装在圆柱形阳极上并围绕第一轴线旋转，同时工件可以是静止的或围绕第二轴线旋转，并且来自电解质溶液的金属沉积在工件上，在工件和阳极之间施加电位差。在本发明的另一实施例中，电镀装置包括与阴极工件间隔开的阳极板。在向阳极板和阴极工件施加电力时，使用设置在电镀装置中的电解液将导电材料沉积在工件表面上，使用具有焊盘或刀片型物体的圆柱形辊。

4. 发明授权

US06437440B1 Thin film metal barrier for electrical interconnections 有权
标题翻译：用于电气互连的薄膜金属屏障
公开(公告)号：US06437440B1
公开(公告)日：2002-08-20
申请号：US09759258
申请日：2001-01-16
申请人： Cyril Cabral, Jr. , Patrick William Dehaven , Daniel Charles Edelstein , David Peter Klaus , James Manley Pollard, III , Carol L. Stanis , Cyprian Emeka Uzoh
发明人： Cyril Cabral, Jr. , Patrick William Dehaven , Daniel Charles Edelstein , David Peter Klaus , James Manley Pollard, III , Carol L. Stanis , Cyprian Emeka Uzoh
IPC分类号： H01L2940
CPC分类号： H01L21/76846 , H01L21/76843 , H01L23/53223 , H01L23/53233 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L24/11 , H01L24/12 , H01L29/4933 , H01L2224/05124 , H01L2224/05181 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10329 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.
摘要翻译：描述了用于电互连的互连结构和阻挡层，其结合了诸如Cu的第一材料和诸如Al，W和PbSn的第二材料之间的六方相中的TaN层。六方相中的TaN多层和α相中的Ta也被描述为阻挡层。本发明克服了在500℃的温度退火期间将Cu扩散到期望分离的材料中的问题。

5. 发明授权

US06355153B1 Chip interconnect and packaging deposition methods and structures 有权
标题翻译：芯片互连和封装沉积方法和结构
公开(公告)号：US06355153B1
公开(公告)日：2002-03-12
申请号：US09398258
申请日：1999-09-17
申请人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
发明人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
IPC分类号： C25D500
CPC分类号： C25D5/00 , C23C18/1608 , C23C18/165 , C23C18/1651 , C23C18/1653 , C23C18/1696 , C23C18/1848 , C23C18/31 , C25D5/02 , C25D5/10 , C25D5/22 , C25D5/34 , H01L21/2885 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76865 , H01L21/76871 , H01L21/76874 , H01L21/76876 , H01L21/76879 , H01L21/76885 , H01L24/11 , H01L2221/1089 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01016 , H01L2924/01019 , H01L2924/01021 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01057 , H01L2924/0106 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/3011
摘要： The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
摘要翻译：本发明涉及一种制造高性能芯片互连和封装的方法，该方法通过提供以更高效和省时的方式在衬底的空腔中沉积导电材料的方法。这是通过从衬底的顶表面选择性地去除种子层的部分，然后在衬底的空腔中沉积导电材料，其中种子层的部分保留在空腔中。另一种方法包括在衬底的顶表面上形成氧化物层，使得导电材料可以沉积在空腔中，而不会在衬底的顶表面上形成材料。本发明还公开了用于形成多级互连的方法和相应的结构。

6. 发明授权

US06333120B1 Method for controlling the texture and microstructure of plated copper and plated structure 失效
标题翻译：控制电镀铜和电镀结构的织构和组织的方法
公开(公告)号：US06333120B1
公开(公告)日：2001-12-25
申请号：US09427703
申请日：1999-10-27
申请人： Patrick William DeHaven , Peter S. Locke , Kenneth P Rodbell , Cyprian Emeka Uzoh
发明人： Patrick William DeHaven , Peter S. Locke , Kenneth P Rodbell , Cyprian Emeka Uzoh
IPC分类号： B32B1500
CPC分类号： C25D5/48 , C25D5/10 , H01L21/2885 , H01L21/76838 , H01L21/76877 , H05K3/385 , Y10T428/12493 , Y10T428/12528
摘要： Copper is plated onto a substrate by plating a layer of copper onto the substrate to provide a maximum thickness of about 350 nanometers, followed by subjecting the copper coated substrate to an oxygen containing gaseous ambient in order to roughen the copper surface. Next, a second layer of copper is electroplated onto the structure to provide the desired thickness. The texture of the second layer of copper is independent of the underlayer of copper and has a random or at least substantially random texture.
摘要翻译：通过将铜层镀在基底上以提供约350纳米的最大厚度，然后将铜涂覆的基底经受含氧气体环境以使粗糙的铜表面，将铜镀在基底上。接下来，将第二层铜电镀到结构上以提供所需的厚度。铜的第二层的纹理与铜的底层无关，并且具有随机或至少基本上随机的纹理。

7. 发明授权

US06228231B1 Electroplating workpiece fixture having liquid gap spacer 有权
标题翻译：具有液隙间隔件的电镀工件夹具
公开(公告)号：US06228231B1
公开(公告)日：2001-05-08
申请号：US09406644
申请日：1999-09-27
申请人： Cyprian Emeka Uzoh
发明人： Cyprian Emeka Uzoh
IPC分类号： C25D1706
CPC分类号： C25D17/06 , C25D7/12 , C25D7/123 , C25D17/001
摘要： A fixture for supporting a workpiece during electroplating of a metal upon the workpiece in a conductive electroplating bath includes a non-conductive frame member for receiving the workpiece therein. The fixture further includes a current distribution means having a plurality of contacts. The plurality of contacts are disposed inwardly for providing an equally distributed electrical contact with an outer perimeter region of the workpiece. The workpiece is supported between the frame member and the current distribution means. Lastly, a thief electrode is perimetrically disposed about the workpiece and spaced a prescribed distance from the workpiece by a gap region. During plating of a metal upon the workpiece, the gap region between the thief and the workpiece is filled with the conductive electroplating bath. An electroplating apparatus having a fixture for supporting a workpiece during an electroplating process and a method of supporting the workpiece to be electroplated are also disclosed.
摘要翻译：用于在导电电镀浴中将金属电镀在工件上时用于支撑工件的夹具包括用于在其中接收工件的非导电框架构件。固定装置还包括具有多个触点的电流分配装置。多个触点被向内设置以提供与工件的外周区域的均匀分布的电接触。工件被支撑在框架构件和电流分配装置之间。最后，窃电电极围绕工件周边设置，并且通过间隙区域与工件隔开规定的距离。在工件上镀金属时，用导电电镀槽填充小偷和工件之间的间隙区域。还公开了一种具有用于在电镀工艺期间支撑工件的固定装置的电镀装置和一种支撑待电镀工件的方法。

8. 发明授权

US6140234A Method to selectively fill recesses with conductive metal 失效
标题翻译：用导电金属选择性填充凹槽的方法
公开(公告)号：US6140234A
公开(公告)日：2000-10-31
申请号：US9824
申请日：1998-01-20
申请人： Cyprian Emeka Uzoh , Stephen Edward Greco
发明人： Cyprian Emeka Uzoh , Stephen Edward Greco
IPC分类号： C25D5/02 , C23C18/31 , C25D7/12 , H01L21/288 , H01L21/3205 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/2885 , H01L21/76807 , H01L21/76865 , H01L21/76873 , H01L21/76879 , H01L2924/0002
摘要： Recesses in a semiconductor structure are selectively plated by providing electrical insulating layer over the semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the barrier layer; depositing and patterning a photoresist layer over the plating seed layer; planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the recesses; removing the photoresist remaining in the recesses; and then electroplating the patterned seed layer with a conductive metal using the barrier layer to carry the current during the electroplating to thereby only plate on the seed layer.In an alternative process, a barrier film is deposited over recesses in an insulator. Then, relatively thick resists are lithographically defined on the field regions, on top of the barrier film over the recesses. A plating base or seedlayer is deposited, so as to be continuous on the horizontal regions of the recesses in the insulator, but discontinuous on their surround wall. The recesses are then plated using the barrier film without seedlayers at the periphery of the substrate wafers for electrical contact. After electroplating, the resist is removed by lift-off process and exposed barrier film is etched by RIE method or by CMP.Also provided is a semiconductor structure obtained by the above processes.
摘要翻译：通过在半导体衬底上和凹槽内提供电绝缘层，然后在绝缘层上形成导电阻挡层来选择性地镀覆半导体结构中的凹陷; 在所述阻挡层上提供电镀种子层; 在所述电镀种子层上沉积和图案化光致抗蚀剂层; 通过去除凹槽之间的晶种层的水平部分来平坦化绝缘水平部分; 去除残留在凹槽中的光致抗蚀剂; 然后使用阻挡层用导电金属电镀图案化种子层，以在电镀期间承载电流，从而仅在种子层上铺板。在替代方法中，阻挡膜沉积在绝缘体中的凹部上。然后，相对厚的抗蚀剂被光刻地限定在场区域上，在阻挡膜上方的凹部上。沉积电镀基底或种子层，以便在绝缘体中的凹部的水平区域上连续地连续，但是在它们的环绕壁上是不连续的。然后，在基板晶片的周边使用阻挡膜将凹槽进行电镀，而不需要用于电接触的晶片的边缘。电镀后，通过剥离工艺除去抗蚀剂，并通过RIE法或CMP蚀刻暴露的阻挡膜。还提供了通过上述方法获得的半导体结构。

9. 发明授权

US5884990A Integrated circuit inductor 失效
标题翻译：形成集成电路环形电感的方法
公开(公告)号：US5884990A
公开(公告)日：1999-03-23
申请号：US949314
申请日：1997-10-14
申请人： Joachim Norbert Burghartz , Daniel Charles Edelstein , Christopher Vincent Jahnes , Cyprian Emeka Uzoh
发明人： Joachim Norbert Burghartz , Daniel Charles Edelstein , Christopher Vincent Jahnes , Cyprian Emeka Uzoh
IPC分类号： H01F17/00 , H01F17/06 , H01F27/28 , H01F30/16 , H01F41/04 , H01L23/522 , H01F5/00 , H01F7/06
CPC分类号： H01L23/5227 , H01F17/0006 , H01F17/0033 , H01F27/2804 , H01F27/2895 , H01F30/16 , H01F41/042 , H01F41/046 , H01F17/06 , H01L2924/0002 , Y10T29/4902
摘要： High quality factor (Q) spiral and toroidal inductor and transformer are disclosed that are compatible with silicon very large scale integration (VLSI) processing, consume a small IC area, and operate at high frequencies. The spiral inductor has a spiral metal coil deposited in a trench formed in a dielectric layer over a substrate. The metal coil is enclosed in ferromagnetic liner and cap layers, and is connected to an underpass contact through a metal filled via in the dielectric layer. The spiral inductor also includes ferromagnetic cores lines surrounded by the metal spiral coil. A spiral transformer is formed by vertically stacking two spiral inductors, or placing them side-by-side over a ferromagnetic bridge formed below the metal coils and cores lines. The toroidal inductor includes a toroidal metal coil with a core having ferromagnetic strips. The toroidal metal coil is segmented into two coils each having a pair of ports to form a toroidal transformer.
摘要翻译：公开了与硅非常大规模集成（VLSI）处理兼容的高质量因子（Q）螺旋和环形电感器和变压器，消耗小的IC区域并在高频下操作。螺旋电感器具有沉积在形成在衬底上的电介质层中的沟槽中的螺旋金属线圈。金属线圈封装在铁磁衬垫和盖层中，并通过电介质层中的金属填充通孔连接到地下通道接触。螺旋电感器还包括由金属螺旋线圈包围的铁磁芯线。通过垂直堆叠两个螺旋电感器或将它们并排放置在形成在金属线圈和芯线下方的铁磁桥上，形成螺旋形变压器。环形电感器包括具有铁磁条的芯的环形金属线圈。环形金属线圈被分成两个线圈，每个线圈具有一对端口以形成环形变压器。

10. 发明授权

US08946899B2 Via in substrate with deposited layer 有权
标题翻译：通过在具有沉积层的衬底中
公开(公告)号：US08946899B2
公开(公告)日：2015-02-03
申请号：US13556339
申请日：2012-07-24
申请人： Cyprian Emeka Uzoh
发明人： Cyprian Emeka Uzoh
IPC分类号： H01L23/48 , H01L21/02
CPC分类号： H01L21/76805 , H01L21/02107 , H01L21/486 , H01L21/76831 , H01L21/76898 , H01L23/15 , H01L23/49827 , H01L2221/1057 , H01L2924/0002 , H01L2924/00
摘要： An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings. The smoothing layer presents a surface smoother than the original interior surface. An insulating layer is formed over the smoothing layer or formed from the smoothing layer, and a conductive element such as a metal is formed in the opening. In a variant, a glass-forming material such as BPSG is applied in the opening. The glass-forming material is reflowed to form a glassy insulating layer which presents a smooth surface. The interface between the metal conductive element and the insulating or glassy layer is smooth, which improves mechanical and electrical properties.
摘要翻译：诸如小直径通孔的开口通过高蚀刻速率工艺形成在诸如单晶硅芯片或晶片的半导体衬底中，这使得开口具有粗糙的内表面。诸如多晶硅层的平滑层被施加在开口的内表面上。平滑层呈现比原始内表面更平滑的表面。在平滑层上形成绝缘层或由平滑层形成，并且在开口中形成诸如金属的导电元件。在一个变型中，在开口中施加诸如BPSG的玻璃形成材料。玻璃形成材料被回流以形成呈现光滑表面的玻璃状绝缘层。金属导电元件与绝缘层或玻璃层之间的界面是光滑的，这提高了机械和电气性能。

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