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1. 发明申请

WO2013075304A1 DUAL CHANNEL POWER SUPPLY WITH TRUE REVERSE CURRENT BLOCKING 审中-公开
标题翻译：双通道电源，具有真正的反向电流阻塞
公开(公告)号：WO2013075304A1
公开(公告)日：2013-05-30
申请号：PCT/CN2011/082758
申请日：2011-11-23
申请人： FAIRCHILD SEMICONDUCTOR (SUZHOU) CO., LTD. , FAIRCHILD SEMICONDUCTOR CORPORATION , HAN, Xinkuan , SUN, Ni , FAN, Jun
发明人： HAN, Xinkuan , SUN, Ni , FAN, Jun
IPC分类号： H02J1/10 , H02M3/155
CPC分类号： H03K17/6874 , H02M1/10
摘要： A power supply system includes a power supply switch (102) including a first input voltage port, a second input voltage port, and an output voltage port; and a comparator circuit (104) configured to compare a first input voltage (V inA ) at the first input voltage port with a second input voltage (V inB ) at the second input voltage port, and select a maximum of the first input voltage and the second input voltage. The comparator circuit (104) is further configured to couple the selected maximum voltage to an n-well region of the power supply switch (102) to block reverse current flow from the output voltage port to the first and the second input voltage ports, and further block reverse current flow from the first input voltage port to the second input voltage port. The system can provide true reverse current blocking and hot swap capability.
摘要翻译：电源系统包括电源开关（102），包括第一输入电压端口，第二输入电压端口和输出电压端口; 以及比较器电路（104），被配置为将所述第一输入电压端口处的第一输入电压（VinA）与所述第二输入电压端口处的第二输入电压（VinB）进行比较，并且选择所述第一输入电压的最大值，输入电压。比较器电路（104）还被配置为将所选择的最大电压耦合到电源开关（102）的n阱区域，以阻止从输出电压端口到第一和第二输入电压端口的反向电流流动;以及进一步阻止从第一输入电压端口到第二输入电压端口的反向电流流动。该系统可提供真正的反向电流阻断和热插拔功能。

2. 发明专利

JP2014093939A Power switching system using control signal driven supply voltage 审中-公开
标题翻译：使用控制信号驱动电源电压的电源开关系统
公开(公告)号：JP2014093939A
公开(公告)日：2014-05-19
申请号：JP2013201720
申请日：2013-09-27
申请人： Fairchild Semiconductor Corp , フェアチャイルド・セミコンダクター・コーポレーション
发明人： JAMES E GILLBERG
IPC分类号： H02J1/00 , F02P3/045 , H02J7/00 , H02M1/00
CPC分类号： F02D41/20 , F02D2041/2051 , F02D2041/2062 , F02D2041/2075 , F02P1/08 , F02P15/02 , H02M2001/0006 , Y10T307/826
摘要： PROBLEM TO BE SOLVED: To provide systems and methods for a power switching system with a switching control circuit powered by a supply voltage derived from an input control signal.SOLUTION: A system may include a power switch configured to electrically couple a device between a battery voltage and a ground, the device to be powered by the battery when the power switch is closed. The system further includes: a control circuit coupled to a gate port of the power switch, and configured to open and close the power switch by adjusting a gate driving signal provided to the gate port in response to a switching control signal provided to the control circuit; and a voltage conditioning circuit configured to generate a supply voltage based on the switching control signal. Thus, the supply voltage powers the control circuit.
摘要翻译：要解决的问题：提供具有由输入控制信号导出的电源供电的开关控制电路的电力开关系统的系统和方法。解决方案：系统可以包括电源开关，电源开关被配置为将电池电连接在电池电压和接地，当电源开关关闭时，设备由电池供电。该系统还包括：控制电路，其耦合到电源开关的门口，并且被配置为响应于提供给控制电路的开关控制信号调整提供给门口的门驱动信号来打开和关闭电源开关 ; 以及电压调节电路，被配置为基于开关控制信号产生电源电压。因此，电源电压为控制电路供电。

3. 发明专利

JP2011223016A Semiconductor die package using lead frame and clip and its manufacturing method 审中-公开
标题翻译：半导体封装使用引线框架和夹子及其制造方法
公开(公告)号：JP2011223016A
公开(公告)日：2011-11-04
申请号：JP2011126306
申请日：2011-06-06
申请人： Fairchild Semiconductor Corp , フェアチャイルドセミコンダクターコーポレイション
发明人： CRUZ AHRWIN VICTOR R , ELSIE CABAHUG , XIANGQI CHIN , IYER BENCAT
IPC分类号： H01L23/50 , H01L23/12
CPC分类号： H01L21/6835 , H01L21/561 , H01L21/568 , H01L23/49548 , H01L23/49551 , H01L23/49562 , H01L24/33 , H01L24/37 , H01L24/39 , H01L24/83 , H01L24/97 , H01L2224/16245 , H01L2224/29109 , H01L2224/29111 , H01L2224/29116 , H01L2224/2919 , H01L2224/32057 , H01L2224/32245 , H01L2224/37147 , H01L2224/73253 , H01L2224/83385 , H01L2224/83801 , H01L2224/8485 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01057 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/12032 , H01L2924/12041 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/19043 , H01L2924/3651 , H01L2224/83 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor die package using a lead frame and a clip which are compatible with an existing package footprint and a pin assignment while having good electrical and thermal performances and its manufacturing method.SOLUTION: A semiconductor die package 100 of this invention includes a main part 14(a), at least one pedestal 14(a)-1 extended from the main part 14(a), a down-set part 14(b) and a lead part 14(c), and manufacturing method of this structure includes a process to obtain a clip structure that the down-set part 14(b) exists between the lead part 14(c) and the main part 14(a), a process to obtain a semiconductor die 16, and a process in which the clip structure 14 is attached to the semiconductor die 16 in such a way that at least one pedestal 14(a)-1 faces against the semiconductor die 16.
摘要翻译：要解决的问题：提供一种使用引线框架和夹子的半导体管芯封装，其与现有封装占地面积和引脚分配兼容，同时具有良好的电气和热性能及其制造方法。解决方案：本发明的半导体管芯封装100包括主要部分14（a），从主要部分14（a）延伸的至少一个基座14（a）-1，下降部分14（b ）和引线部分14（c），并且该结构的制造方法包括获得在引线部分14（c）和主体部分14（a）之间存在下降部分14（b）的夹子结构的工艺），获得半导体管芯16的工艺，以及夹具结构14以至少一个基座14（a）-1面向半导体管芯16的方式附接到半导体管芯16的工艺。 P>版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2003209067A SEMICONDUCTOR DEVICE AND METHOD OF FORMING ELECTRICAL CONNECTION OF SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003209067A
公开(公告)日：2003-07-25
申请号：JP2002369665
申请日：2002-12-20
申请人： FAIRCHILD SEMICONDUCTOR
发明人： WOODIN RICHARD L , SENG WILLIAM F
IPC分类号： H01L21/28 , H01L21/04 , H01L29/24 , H01L29/45
摘要： PROBLEM TO BE SOLVED: To provide an ohmic contact point of low resistance to a broad band gap layer. SOLUTION: A semiconductor device which includes a contact point material that contacts continuously with a contact point region. In one embodyment, the contact point region 50 is made of an alloy which is composed of a broad band gap material and a low melting point contact point material. The broad band gap material is made of silicon carbide, and the low melting point contact point material is made of aluminum. In another embodyment, an uniform ohmic contact point between a contact point material and a semiconductor material is formed by annealing the contact point at the melting point temperature of the contact point material or below. In one embodyment, the contact point is annealed for 5 hours or more. COPYRIGHT: (C)2003,JPO

5. 发明专利

JP2003204026A SEMICONDUCTOR DEVICE INCLUDING MOLDED WIRELESS EXPOSED DRAIN PACKAGING 审中-公开
公开(公告)号：JP2003204026A
公开(公告)日：2003-07-18
申请号：JP2002313501
申请日：2002-09-20
申请人： FAIRCHILD SEMICONDUCTOR
发明人： QUINONES MARIA C Y , TANGPUZ CONSUELO N
IPC分类号： H01L23/34 , H01L23/48 , H01L23/50
摘要： PROBLEM TO BE SOLVED: To package an element, e.g. a power switching device, with high reliability using a lead frame. SOLUTION: The semiconductor device includes a lead frame (20) and a die (23) coupled thereto. A drain pad (50) is coupled to the drain region of the die in a body that substantially envelopes the lead frame and the die. The body is placed around the lead frame and the die such that a surface of the drain pad opposite the die is exposed through the window. COPYRIGHT: (C)2003,JPO

6. 发明专利

JP2001237329A MOS TRANSISTOR STRUCTURE WITH PEDESTAL FOR ESD PROTECTION AND METHOD OF MANUFACTURING THE SAME 失效
公开(公告)号：JP2001237329A
公开(公告)日：2001-08-31
申请号：JP2000352669
申请日：2000-11-20
申请人： FAIRCHILD SEMICONDUCTOR
发明人： SUGERMAN ALVIN
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/092 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a device suitable for an ESD protection device of a MOS transistor base that can provide protection from voltage deviation generated in a certain range. SOLUTION: The ESD protection device of the present invention includes a transistor structure having trenched active regions, and a pedestal gate region is formed. The active regions are positioned below a level corresponding to a level of an interface 32 between a gate oxide and an epitaxial surface by etching to a selectable depth. Subsequently, higher charge carrier concentrations can be established at a position distant from the interface between the gate oxide and the epitaxial layer by implanting an appropriate dopant to the active regions. In particular, by positioning a transistor channel much further below this interface, occurrence of a hot spot due to the highest-concentration dopant made adjacent to an insulating oxide layer can be minimized.

7. 发明专利

JP2001136737A NO-LOSS CURRENT DETECTION IN BACKUP CONVERTER OPERATED WITH LOW-IMPACT COEFFICIENT AND HIGH CLOCK FREQUENCY 失效
公开(公告)号：JP2001136737A
公开(公告)日：2001-05-18
申请号：JP2000296683
申请日：2000-09-28
申请人： FAIRCHILD SEMICONDUCTOR
发明人： ROSSETTI NAZZARENO , SANDERS SETH
IPC分类号： H02M3/155 , H02M3/158
摘要： PROBLEM TO BE SOLVED: To realize a converter, which is operated with a high frequency and a low-impact coefficient and converts high voltage into low voltage. SOLUTION: A high-potential side switch and a low potential side switch are connected in series between an input voltage and the ground potential. An inductor and a capacitor are connected between the junction of both the switches and a load so as to compose a low-pass filter. The two switches are turned on and off complementarily, to control the charging period and discharging period of the filter in order to obtain a required output voltage. A 'trough current control' method, where current applied to the low potential side switch is monitored, and if the current is lowered to a value which is not higher than a predetermined reference value, the discharging period is finished and the charging period is started is employed, to realize a stable operation with a low impact coefficient.

8. 发明专利

JP2001042980A BUS HOLD CIRCUIT WITH OVERVOLTAGE RESISTANCE 失效
公开(公告)号：JP2001042980A
公开(公告)日：2001-02-16
申请号：JP2000164881
申请日：2000-06-01
申请人： FAIRCHILD SEMICONDUCTOR
发明人： MORRILL DAVID P
IPC分类号： G06F3/00 , H03K3/037 , H03K3/356
摘要： PROBLEM TO BE SOLVED: To provide a bus hold circuit which is composed only of a CMOS having an active system for dissolving an overvoltage state. SOLUTION: In conventional constitution, this bus hold circuit includes a sense circuit 30 and an arbiter circuit 40 which stop an overvoltage from affecting a latch inverter. The sense circuit includes a comparator so designed as to compare the potential of a standard high-potential power source with the potential of a signal applied to an input node of the bus hold circuit. The arbiter circuit is biased by using the potential which is higher between the two potentials and then couples the high potential with an artificial high-potential power rail. The artificial high-potential power rail electrifies the latch inverter so that the latch inverter will not be biased in the overvoltage state.

9. 发明专利

JP2000194429A METHOD AND CIRCUIT FOR PREVENTING OSCILLATION OF BATTERY CHARGER 失效
公开(公告)号：JP2000194429A
公开(公告)日：2000-07-14
申请号：JP36507899
申请日：1999-12-22
申请人： FAIRCHILD SEMICONDUCTOR
发明人： RONALD J LENK , STEPHEN W BRISON
IPC分类号： H02J7/10 , G05F1/10 , H02J7/00
摘要： PROBLEM TO BE SOLVED: To eliminate the delay of the battery charger and to prevent oscillation trends by clamping the output of an error amplifier and eliminating conditions where the error amplifier is saturated. SOLUTION: The output of the error amplifier is clamped to eliminate the conditions where the error amplifier is saturated and then the possibility of an overshoot of a current is eliminated. This battery charger uses the output of an operation error amplifier to clamp other amplifiers with a little higher voltage. In a cross-clamping circuit 206, a diode 212 connects the output of a current error amplifier 202 to the output of a voltage error amplifier 200 through a unity gain buffer amplifier 214. Similarly, the output of the voltage error amplifier 200 is connected to the output of the current error amplifier 202 through a diode 216 and a unity gain buffer amplifier 218. Therefore, the output of an amplifier in a nonoperation state has its voltage set higher by one diode than the output of an amplifier in an operation state.

10. 发明专利

JP2000138571A SWITCHING NOISE REDUCING CIRCUIT 失效
公开(公告)号：JP2000138571A
公开(公告)日：2000-05-16
申请号：JP23275799
申请日：1999-08-19
申请人： FAIRCHILD SEMICONDUCTOR
发明人： MORRILL DAVID
IPC分类号： H01L21/822 , H01L27/04 , H03F3/30 , H03K17/16 , H03K19/003 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To provide a buffer circuit which can reduce the noise which is produced when signal switching is performed without sacrificing the transmitting speed of the circuit. SOLUTION: An output buffer 10 contains a first clamp circuit 20 connected to the pull-up output transistor of the buffer to and a second clamp circuit 30 connected to the pull-down output transistor of the buffer 10. Each clamp circuit contains a selectable delay stage coupled with the output of the buffer 10, a current regulator which is controlled by the delay stage, and a clamp device coupled with the control node of the connected output transistor. When the current regulator is conducted, the control node of the output transistor is clamped to a potential close to the turning-on threshold of the node.

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