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1. 发明授权

US08170487B2 Baseband transmitter self-jamming and intermodulation cancellation device 有权
标题翻译：基带发射机自动干扰和互调消除装置
公开(公告)号：US08170487B2
公开(公告)日：2012-05-01
申请号：US11346888
申请日：2006-02-03
申请人： Gurkanwal S. Sahota , Christos Komninakis
发明人： Gurkanwal S. Sahota , Christos Komninakis
IPC分类号： H04B1/00
CPC分类号： H04B1/525 , H04B1/10
摘要： Some embodiments provide a method, system, and apparatus for interference cancellation at the baseband of a receiver. A wireless communication device, having a transmitter and receiver, is provided with an adaptive circuit that cancels interference caused by transmit signals (or other signals) leaked or bled onto the receiver at baseband to facilitate detection of a received signal of interest. Some implementations provide for a circuit that approximately reconstructs the second and third order components caused by the nonlinear response of the down-conversion chain of a receiver. This reconstructed signal is then subtracted from the composite received signal to obtain a received signal of interest.
摘要翻译：一些实施例提供了用于接收机基带处的干扰消除的方法，系统和装置。具有发射机和接收机的无线通信设备设置有自适应电路，该自适应电路消除由基带泄露或流出到接收机上的发射信号（或其他信号）引起的干扰，以便于检测到所接收到的感兴趣的信号。一些实施方案提供了近似重建由接收机的下变换链的非线性响应引起的第二和第三阶分量的电路。然后从复合接收信号中减去该重建的信号，以获得感兴趣的接收信号。

2. 发明申请

US20110133794A1 PHASE LOCKED LOOP WITH DIGITAL COMPENSATION FOR ANALOG INTEGRATION 有权
标题翻译：用于模拟集成的数字补偿的相位锁定环
公开(公告)号：US20110133794A1
公开(公告)日：2011-06-09
申请号：US12632053
申请日：2009-12-07
申请人： JEREMY D. DUNWORTH , GARY J. BALLANTYNE , BHUSHAN S. ASURI , JIFENG GENG , GURKANWAL S. SAHOTA
发明人： JEREMY D. DUNWORTH , GARY J. BALLANTYNE , BHUSHAN S. ASURI , JIFENG GENG , GURKANWAL S. SAHOTA
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L7/093
摘要： A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).
摘要翻译：锁相环（PLL）装置包括数字微分器，其被配置为区分数字环路信号以至少部分地补偿模拟积分器对模拟电流信号的积分。数模转换器（DAC）包括基于数字输入信号产生模拟电流信号的电流源输出级。模拟积分器对模拟电流信号进行积分，以产生用于控制压控振荡器（VCO）的电压控制信号。

3. 发明申请

US20080129398A1 HIGH RESOLUTION DIGITALLY CONTROLLED OSCILLATOR 有权
标题翻译：高分辨率数字控制振荡器
公开(公告)号：US20080129398A1
公开(公告)日：2008-06-05
申请号：US11565523
申请日：2006-11-30
申请人： Bo Sun , Arun Jayaraman , Gary John Ballantyne , Gurkanwal S. Sahota
发明人： Bo Sun , Arun Jayaraman , Gary John Ballantyne , Gurkanwal S. Sahota
IPC分类号： H03B5/08 , H03B5/18
CPC分类号： H03L7/10 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H03L7/099
摘要： This disclosure describes designs for a digitally controlled oscillator (DCO). The DCO can overcome many of the shortcomings associated with conventional voltage controlled oscillators (VCOs), and may improve wireless communication devices. The described DCO may improve the frequency synthesis process, reduce noise in a wireless communication device, and allow for simplification of various components of the device.
摘要翻译：本公开描述了数字控制振荡器（DCO）的设计。 DCO可以克服与常规压控振荡器（VCO）相关的许多缺点，并且可以改进无线通信设备。所描述的DCO可以改善频率合成过程，减少无线通信设备中的噪声，并且允许简化设备的各种组件。

4. 发明授权

US5880631A High dynamic range variable gain amplifier 失效
标题翻译：高动态范围可变增益放大器
公开(公告)号：US5880631A
公开(公告)日：1999-03-09
申请号：US789108
申请日：1997-01-27
申请人： Gurkanwal S. Sahota
发明人： Gurkanwal S. Sahota
IPC分类号： H03G1/00 , H03G3/30
CPC分类号： H03G1/0023
摘要： A multi-stage low power, high dynamic range variable gain amplifier comprises an input stage cascaded with one or more current amplifier stages, whereby the gain of each stage may be independently controlled. The input stage may be comprised of a variable transconductance amplifier using variable emitter degeneration. The current amplifier may be comprised of a differential Darlington amplifier coupled to a differential cascode amplifier. The transconductance amplifier converts an input voltage signal to a current signal. The variable gain amplifier is designed for efficient low power operation.
摘要翻译：多级低功率，高动态范围可变增益放大器包括与一个或多个电流放大器级级联的输入级，由此可以独立地控制每级的增益。输入级可以由使用可变发射极退化的可变跨导放大器组成。电流放大器可以由耦合到差分共源共栅放大器的差分达林顿放大器组成。跨导放大器将输入电压信号转换为电流信号。可变增益放大器专为有效的低功耗操作而设计。

5. 发明授权

US08385854B2 Adaptive parametric power amplifier protection circuit 有权
标题翻译：自适应参数功率放大器保护电路
公开(公告)号：US08385854B2
公开(公告)日：2013-02-26
申请号：US12470418
申请日：2009-05-21
申请人： Aristotele Hadjichristos , Gurkanwal S. Sahota
发明人： Aristotele Hadjichristos , Gurkanwal S. Sahota
IPC分类号： H01Q11/12 , H04B1/04 , H03G3/10
CPC分类号： H04B1/0466 , H03F1/523 , H03F3/24 , H03F2200/447 , H03F2200/468
摘要： A device including a gain control element coupled prior to or within a radio frequency (RF) power amplifier (PA) with an adaptive parametric PA protection circuit is described. In an exemplary embodiment, the device includes a gain control element coupled prior to a radio frequency power amplifier with a power stage with corresponding transistor breakdown threshold values, having an adaptive parametric PA protection circuit configured to receive at least one power stage drain-source voltage parameter value, at least one power stage drain-gate voltage parameter value, and at least one power stage drain-source current parameter value, and including an adaptive parametric PA protection circuit having a first section for processing the parameter values and a second section for generating a gain correction signal to adjust the gain control element with optimal power added efficiency (PAE) for the power stage within the corresponding transistor breakdown threshold values.
摘要翻译：描述了在具有自适应参数PA保护电路的射频（RF）功率放大器（PA）之前或之内耦合的增益控制元件的装置。在示例性实施例中，该装置包括增益控制元件，该增益控制元件在具有相应晶体管击穿阈值的功率级的射频功率放大器之前耦合，具有自适应参数PA保护电路，该自适应参数PA保护电路被配置为接收至少一个功率级漏 - 源电压参数值，至少一个功率级漏极栅极电压参数值和至少一个功率级漏源电流参数值，并且包括具有用于处理参数值的第一部分的自适应参数PA保护电路和用于产生增益校正信号，以在相应的晶体管击穿阈值内对功率级的最佳功率附加效率（PAE）调节增益控制元件。

6. 发明授权

US07826816B2 Systems, methods, and apparatus for frequency conversion 有权
标题翻译：用于频率转换的系统，方法和装置
公开(公告)号：US07826816B2
公开(公告)日：2010-11-02
申请号：US11531314
申请日：2006-09-13
申请人： Wei Zhuo , Aristotele Hadjichristos , Gurkanwal S. Sahota , Solti Peng
发明人： Wei Zhuo , Aristotele Hadjichristos , Gurkanwal S. Sahota , Solti Peng
IPC分类号： H04B1/26
CPC分类号： H03D7/166 , H03H19/008 , H03H2007/0192
摘要： A method according to one embodiment includes using a quadrature set of local oscillator signals having duty cycles of substantially less than fifty percent to perform a mixing operation on a radio-frequency current signal. Other embodiments include using a quadrature set of local oscillator signals having duty cycles of less than twenty-five percent.
摘要翻译：根据一个实施例的方法包括使用具有基本上小于百分之五十的占空比的本地振荡器信号的正交组来对射频电流信号执行混频操作。其他实施例包括使用占空比小于百分之二十五的本地振荡器信号的正交集合。

7. 发明授权

US08411788B2 Digital transmitters for wireless communication 有权
标题翻译：用于无线通信的数字发射机
公开(公告)号：US08411788B2
公开(公告)日：2013-04-02
申请号：US11561262
申请日：2006-11-17
申请人： Gurkanwal S Sahota
发明人： Gurkanwal S Sahota
IPC分类号： H04L27/00
CPC分类号： H04L27/361 , H03C5/00 , H03D13/00 , H03F1/0205 , H03F3/217 , H03F3/245 , H03F2200/321 , H03F2200/331 , H03F2200/336 , H03F2200/451 , H03F2200/456
摘要： Digital transmitters having improved characteristics are described. In one design of a digital transmitter, a first circuit block receives inphase and quadrature signals, performs conversion from Cartesian to polar coordinates, and generates magnitude and phase signals. A second circuit block (which may include a delta-sigma modulator or a digital filter) generates an envelope signal based on the magnitude signal. A third circuit block generates a phase modulated signal based on the phase signal. The third circuit block may include a phase modulating phase locked loop (PLL), a voltage controlled oscillator (VCO), a saturating buffer, and so on. A fourth circuit block (which may include one or more exclusive-OR gates or an amplifier with multiple gain states) generates a digitally modulated signal based on the envelope signal and the phase modulated signal. A fifth circuit block (which may include a class D amplifier and/or a power amplifier) amplifies the digitally modulated signal and generates an RF output signal.
摘要翻译：描述了具有改进特性的数字发射机。在数字发射机的一种设计中，第一电路块接收同相和正交信号，执行从笛卡尔坐标转换为极坐标，并产生幅度和相位信号。第二电路块（其可以包括Δ-Σ调制器或数字滤波器）基于幅度信号产生包络信号。第三电路块基于相位信号产生相位调制信号。第三电路块可以包括相位调制锁相环（PLL），压控振荡器（VCO），饱和缓冲器等。第四电路块（其可以包括一个或多个异或门或具有多个增益状态的放大器）基于包络信号和相位调制信号产生数字调制信号。第五电路块（其可以包括D类放大器和/或功率放大器）放大数字调制信号并产生RF输出信号。

8. 发明申请

US20080309537A1 PSEUDO-DIFFERENTIAL CLASS-AB DIGITAL-TO-ANALOG CONVERTER WITH CODE DEPENDENT DC CURRENT 有权
标题翻译：具有代码直流电流的PSEUDO-DIFFERENTIAL CLASS-AB数字到模拟转换器
公开(公告)号：US20080309537A1
公开(公告)日：2008-12-18
申请号：US11762884
申请日：2007-06-14
申请人： Dongwon Seo , Bo Sun , Gurkanwal S. Sahota , Manu Mishra
发明人： Dongwon Seo , Bo Sun , Gurkanwal S. Sahota , Manu Mishra
IPC分类号： H03M1/66
CPC分类号： H03M1/002 , H03M1/682 , H03M1/747
摘要： A digital-to-analog converter, RF transmit channel and method, for converting a digital signal of N bits having a set M of most significant bits and a set L of least significant bits to an analog signal, are disclosed. The digital signal defines a set of coded values which are converted to analog values and modulated on to a RF signal. The digital-to-analog converter includes a plurality of switches and an output stage, for providing at least a first differential output signal and a second differential output signal. The output stage modifies currents received from the plurality of switches, such that the value of the average output current of the first and second differential outputs signals is steered to a relatively low current value at the mid-point of the coded values.
摘要翻译：公开了用于将具有最高有效位的集合M的N位的数字信号和最低有效位的集合L转换为模拟信号的数模转换器，RF发送信道和方法。数字信号定义了一组编码值，它们被转换为模拟值并被调制到RF信号上。数模转换器包括多个开关和输出级，用于至少提供第一差分输出信号和第二差分输出信号。输出级修改从多个开关接收的电流，使得第一和第二差分输出信号的平均输出电流的值被转向在编码值的中点处的相对低的电流值。

9. 发明申请

US20080014896A1 SYSTEMS, METHODS, AND APPARATUS FOR FREQUENCY CONVERSION 有权
标题翻译：用于频率转换的系统，方法和装置
公开(公告)号：US20080014896A1
公开(公告)日：2008-01-17
申请号：US11531314
申请日：2006-09-13
申请人： Wei Zhuo , Aristotele Hadjichristos , Gurkanwal S. Sahota , Solti Peng
发明人： Wei Zhuo , Aristotele Hadjichristos , Gurkanwal S. Sahota , Solti Peng
IPC分类号： H04B1/26
CPC分类号： H03D7/166 , H03H19/008 , H03H2007/0192
摘要： A method according to one embodiment includes using a quadrature set of local oscillator signals having duty cycles of substantially less than fifty percent to perform a mixing operation on a radio-frequency current signal. Other embodiments include using a quadrature set of local oscillator signals having duty cycles of less than twenty-five percent.
摘要翻译：根据一个实施例的方法包括使用具有基本上小于百分之五十的占空比的本地振荡器信号的正交组来对射频电流信号执行混频操作。其他实施例包括使用占空比小于百分之二十五的本地振荡器信号的正交集合。

10. 发明授权

US09559639B2 Protection circuit for power amplifier 有权
标题翻译：功率放大器保护电路
公开(公告)号：US09559639B2
公开(公告)日：2017-01-31
申请号：US12715250
申请日：2010-03-01
申请人： Wenjun Su , Aristotele Hadjichristos , Gurkanwal S. Sahota , Marco Cassia
发明人： Wenjun Su , Aristotele Hadjichristos , Gurkanwal S. Sahota , Marco Cassia
IPC分类号： H04B1/04 , H03F1/52 , H03F3/24 , H03G3/30
CPC分类号： H03F1/52 , H03F3/24 , H03F2200/435 , H03F2200/78 , H03G3/3042 , H04B2001/0408
摘要： Techniques for protecting a power amplifier (PA) are described. In an exemplary design, an apparatus includes (i) a PA module to amplify an input RF signal and provide an output RF signal and (ii) a protection circuit to control a transmitter gain to protect the PA module against high peak voltage. In an exemplary design, the protection circuit includes a set of comparators to quantize an analog input signal and provide digital comparator output signals used to adjust the transmitter gain. In another exemplary design, the protection circuit reduces and increases the transmitter gain with hysteresis. In yet another exemplary design, the protection circuit has faster response to rising amplitude than falling amplitude of the output RF signal. The hysteresis and/or the different rise and fall responses may allow the protection circuit to avoid toggling the transmitter gain under severe load mismatch and to handle time-varying envelope due to amplitude modulation.
摘要翻译：描述了用于保护功率放大器（PA）的技术。在示例性设计中，装置包括（i）PA模块，用于放大输入RF信号并提供输出RF信号，以及（ii）保护电路以控制发射机增益以保护PA模块免受高峰值电压。在示例性设计中，保护电路包括一组比较器，用于量化模拟输入信号并提供用于调整发射机增益的数字比较器输出信号。在另一示例性设计中，保护电路通过滞后减小并增加发射机增益。在又一示例性设计中，保护电路比对输出RF信号的下降幅度具有对振幅上升的响应更快。迟滞和/或不同的上升和下降响应可以允许保护电路避免在严重负载不匹配的情况下切换发射机增益，并且由于幅度调制来处理时变包络。

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