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1. 发明授权

US07569468B2 Method for forming a floating gate memory with polysilicon local interconnects 失效
标题翻译：用于形成具有多晶硅局部互连的浮动栅极存储器的方法
公开(公告)号：US07569468B2
公开(公告)日：2009-08-04
申请号：US11217624
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/3205
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

2. 发明申请

US20080089647A1 RESONATOR FOR THERMO OPTIC DEVICE 有权
标题翻译：热电偶装置谐振器
公开(公告)号：US20080089647A1
公开(公告)日：2008-04-17
申请号：US11951796
申请日：2007-12-06
申请人： Gurtej Sandhu , Guy Blalock , Howard Rhodes
发明人： Gurtej Sandhu , Guy Blalock , Howard Rhodes
IPC分类号： G02B6/26
CPC分类号： G02B6/132 , G02B6/12004 , G02B6/12007 , G02B6/136 , G02F1/011 , G02F1/0147 , G02F2203/15
摘要： A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is formed on a surface of the lower cladding. Since upper surfaces of the resonator and waveguide are substantially coplanar, the aspect ratio, as between the waveguide and resonator in an area where the waveguide and resonator front one another, decreases thereby increasing the bandwidth of the resonator. The depression is formed by photomasking and etching the lower cladding before forming the resonator and waveguide. Pluralities of resonators are also taught that are formed in a plurality of depressions of the lower cladding. To decrease resonator bandwidth, waveguide(s) are formed in the depression(s) of the lower cladding while the resonator is formed on the surface. Thermo optic devices formed with these resonators are also taught.
摘要翻译：用于热光器件的谐振器以与波导相同的工艺步骤形成，并且形成在下包层的凹陷中，同时波导形成在下包层的表面上。由于谐振器和波导的上表面基本上是共面的，因此在波导和谐振器彼此前向的区域中的波导和谐振器之间的纵横比减小，从而增加了谐振器的带宽。在形成谐振器和波导之前，通过光掩模和蚀刻下部包层形成凹陷。还教导了形成在下部包层的多个凹部中的多个谐振器。为了减小谐振器带宽，当在表面上形成谐振器时，在下包层的凹陷中形成波导。还教导了用这些谐振器形成的热光器件。

3. 发明申请

US20060258113A1 CAPACITOR STRUCTURE 审中-公开
标题翻译：电容结构
公开(公告)号：US20060258113A1
公开(公告)日：2006-11-16
申请号：US11460021
申请日：2006-07-26
申请人： Gurtej Sandhu , Guy Blalock
发明人： Gurtej Sandhu , Guy Blalock
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L27/10852 , H01L21/02183 , H01L21/02197 , H01L21/022 , H01L21/02271 , H01L21/31637 , H01L21/31654 , H01L27/10811 , H01L27/11507 , H01L28/55 , H01L28/56 , H01L28/65 , H01L28/91
摘要： A capacitor structure and method of forming it are described. In particular, a high-K dielectric oxide is provided as the capacitor dielectric. The high-K dielectric is deposited in a series of thin layers and oxidized in a series of oxidation steps, as opposed to a depositing a single thick layer. Further, at least one of the oxidation steps is less aggressive than the oxidation environment or environments that would be used to deposit the single thick layer. This allows greater control over oxidizing the dielectric and other components beyond the dielectric.
摘要翻译：描述电容器结构及其形成方法。特别地，提供高K电介质氧化物作为电容器电介质。与沉积单个厚层相反，高K电介质沉积在一系列薄层中并在一系列氧化步骤中被氧化。此外，至少一个氧化步骤比用于沉积单个厚层的氧化环境或环境更不具有侵蚀性。这允许更好地控制电介质和超过电介质的其它组件的氧化。

4. 发明申请

US20060228084A1 RESISTIVE HEATER FOR THERMO OPTIC DEVICE 有权
标题翻译：热电器件电阻式加热器
公开(公告)号：US20060228084A1
公开(公告)日：2006-10-12
申请号：US11424401
申请日：2006-06-15
申请人： Gurtej Sandhu , Guy Blalock
发明人： Gurtej Sandhu , Guy Blalock
IPC分类号： G02B6/10
CPC分类号： G02B6/125 , G02F1/0102 , G02F1/0147 , G02F1/2257 , G02F2201/30 , G02F2201/307 , G02F2202/104
摘要： Resistive heaters formed in two mask counts on a surface of a grating of a thermo optic device thereby eliminating one mask count from prior art manufacturing methods. The resistive heater is comprised of a heater region and a conductive path region formed together in a first mask count from a relatively high resistance material. A conductor formed from a relatively low resistance material is formed directly on the conductive path region in a second mask count. Thermo optic devices formed by these two mask count methods are also described.
摘要翻译：在热光器件的光栅的表面上形成两个掩模计数的电阻加热器，从而从现有技术的制造方法中消除一个掩模计数。电阻加热器包括加热器区域和形成在来自相对高电阻材料的第一掩模计数中的导电路径区域。由相对低电阻材料形成的导体以第二掩模计数直接形成在导电路径区域上。还描述了通过这两种掩模计数方法形成的热光学器件。

5. 发明申请

US20060008963A1 Method for forming polysilicon local interconnects 审中-公开
公开(公告)号：US20060008963A1
公开(公告)日：2006-01-12
申请号：US11217950
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

6. 发明申请

US20060006455A1 Memory cell with polysilicon local interconnects 审中-公开
标题翻译：具有多晶硅局部互连的存储单元
公开(公告)号：US20060006455A1
公开(公告)日：2006-01-12
申请号：US11218100
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L29/788 , H01L23/52
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

7. 发明申请

US20050287816A1 Methods of forming patterned photoresist layers over semiconductor substrates 有权
标题翻译：在半导体衬底上形成图案化光致抗蚀剂层的方法
公开(公告)号：US20050287816A1
公开(公告)日：2005-12-29
申请号：US10879367
申请日：2004-06-28
申请人： Guy Blalock , Gurtej Sandhu , Jon Daley
发明人： Guy Blalock , Gurtej Sandhu , Jon Daley
IPC分类号： G03F7/09 , H01L21/027 , H01L21/31 , H01L21/469 , H01L21/4763 , H01L21/768
CPC分类号： G03F7/091 , H01L21/0276
摘要： This invention includes methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a porous antireflective coating is formed over a semiconductor substrate. A photoresist footer-reducing fluid is provided within pores of the porous antireflective coating. A positive photoresist is formed over the porous antireflective coating having the fluid therein. The positive photoresist is patterned and developed to form a patterned photoresist layer, with the fluid within the pores being effective to reduce photoresist footing in the patterned photoresist layer than would otherwise occur in the absence of the fluid within the pores. Other aspects and implementations are contemplated.
摘要翻译：本发明包括在半导体衬底上形成图案化光致抗蚀剂层的方法。在一个实施方案中，在半导体衬底上形成多孔抗反射涂层。在多孔抗反射涂层的孔内提供光致抗蚀剂页脚还原液。在其中具有流体的多孔抗反射涂层上形成正性光致抗蚀剂。正性光致抗蚀剂被图案化和显影以形成图案化的光致抗蚀剂层，孔内的流体有效地减少图案化光致抗蚀剂层中的光致抗蚀剂底脚，而不是在孔内不存在流体的情况下发生。考虑了其他方面和实现。

8. 发明申请

US20050208730A1 Methods of forming materials within openings, and methods of forming isolation regions 有权
公开(公告)号：US20050208730A1
公开(公告)日：2005-09-22
申请号：US11115833
申请日：2005-04-25
申请人： John Moore , Guy Blalock
发明人： John Moore , Guy Blalock
IPC分类号： H01L21/3105 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76235 , H01L21/31053
摘要： In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending therethrough to expose a portion of the underlying substrate and comprising an upper corner at a periphery of the opening, the upper corner having a corner angle with a first degree of sharpness; b) reducing the sharpness of the corner angle to a second degree; c) after reducing the sharpness, forming a layer of material within the opening and over the etch-stop layer; and d) planarizing the material with a method selective for the material relative to the etch-stop layer to remove the material from over the etch-stop layer while leaving the material within the opening.

9. 发明申请

US20050098448A1 Detection of gas phase materials 审中-公开
公开(公告)号：US20050098448A1
公开(公告)日：2005-05-12
申请号：US11014618
申请日：2004-12-16
申请人： Guy Blalock
发明人： Guy Blalock
IPC分类号： G01N27/04 , G01N33/00 , C12Q1/70 , G01F1/64 , G08B17/12
CPC分类号： G01N27/125
摘要： Sensors and methods of monitoring for the presence of gas phase materials by detecting the formation of films based on the gas phase material are disclosed. Advantageously, some gas phase materials preferentially deposit on specific surfaces. As a result, selective detection of those gas phase materials can be obtained by detecting films deposited on those detection surfaces. Examples of gas phase materials that may be detected include RuO4, IrO4 and RhO4.

10. 发明授权

US06827824B1 Enhanced collimated deposition 失效
标题翻译：增强准直沉积
公开(公告)号：US06827824B1
公开(公告)日：2004-12-07
申请号：US08631465
申请日：1996-04-12
申请人： Guy Blalock , Gurtej S. Sandhu
发明人： Guy Blalock , Gurtej S. Sandhu
IPC分类号： C23C1435
CPC分类号： C23C14/345 , C23C14/351 , C23C14/354 , H01J37/32339 , H01J2237/3327
摘要： An apparatus for film deposition onto a substrate from a source of target particles including a plasma generator creating a plasma that isotropically accelerates the target particles towards the substrate. A secondary ionizer creates a secondary ionization zone between the plasma and the substrate support. The isotropically accelerated target particles are ionized as they pass through the secondary ionization zone. A static field generator creates a static field between the secondary ionization zone and the substrate accelerating the ionized target particles along a substantially collimated trajectory perpendicular to the substrate. Optionally, a collimator is included between the secondary ionization zone and the substrate and biased to focus and accelerate the collimated target particles.
摘要翻译：一种用于从包括等离子体发生器的目标粒子源在基底上沉积膜的装置，其产生等离子体，所述等离子体将目标颗粒各向同性地加速到衬底。二次电离器在等离子体和衬底支撑件之间产生二次电离区。各向同性加速的目标颗粒在通过二次电离区时被电离。静电场发生器在二次电离区和基板之间产生静电场，该静电场沿垂直于衬底的基本上准直的轨迹加速电离的靶颗粒。可选地，准直仪包括在二次电离区和衬底之间，并被偏置以聚焦并加速准直的靶颗粒。

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