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1. 发明专利

JP2020091868A 作業負荷の繰り返し冗長化审中-公开
公开(公告)号：JP2020091868A
公开(公告)日：2020-06-11
申请号：JP2019218908
申请日：2019-12-03
申请人： IMAGINATION TECH LTD
发明人： DAMIEN MCNAMARA , JAMIE BROOME , IAN KING , WEI SHAO , MARIO SOPENA NOVALES , DILIP BANSAL
IPC分类号： G06F11/16 , G06F15/80 , G06T15/00
摘要：【課題】データ処理ハードウェアで安全目標を達成するために、チップ面積や消費電力を増加させない。【解決手段】グラフィック処理システムにおいて、グラフィック処理ユニット200は、タスクを処理するための複数の処理ユニット204と、チェックユニットと、フォルト検出ユニットと、を含む。グラフィック処理ユニットが、第1および第2の処理された出力をそれぞれ生成するために、複数の処理ユニットで構成されており、チェックユニットが、それぞれ第1および第2の処理された出力の特性である、第1および第2のシグネチャを形成する。フォルト検出ユニットは、第1および第2のシグネチャを比較し、第1および第2のシグネチャが一致しない場合に、フォルト信号を発生させる。【選択図】図2

2. 发明公开

KR20200139788A 데이터 변환 파이프라인용 하드웨어 설계 검증 审中-公开
公开(公告)号：KR20200139788A
公开(公告)日：2020-12-14
申请号：KR20207031916
申请日：2019-04-04
申请人： IMAGINATION TECH LTD
发明人： ELLIOTT SAM
IPC分类号： G06F30/3323 , G01R31/3183 , G06F119/12
摘要： 하나이상의데이터변환요소를포함한데이터변환파이프라인용하드웨어설계를공식검증을통해검증하기위한방법및 시스템으로서, 하나이상의입력에대한데이터변환을수행하되, 공식검증은, 공식검증툴이수행해야하는데이터변환계산을단순화하는조건하에서수행된다. 일구현예에서, 공식검증동안에기능요소가동일한입력에대해동일한출력을생성하도록공식검증툴에의해조합입력의피평가기능으로처리된기능요소로하드웨어설계의데이터변환요소중 하나이상을대체하는단계, 및트랜잭션세트의각 트랜잭션에대해데이터변환파이프라인용수정하드웨어설계의인스턴스가, 그트랜잭션에대해하나이상의출력기준세트와매칭하는지공식검증하는단계에의해, 데이터변환파이프라인용하드웨어설계를검증한다.

3. 发明公开

KR20200139235A 데이터 변환 파이프라인용 하드웨어 설계 검증 审中-公开
公开(公告)号：KR20200139235A
公开(公告)日：2020-12-11
申请号：KR20207031790
申请日：2019-04-04
申请人： IMAGINATION TECH LTD
发明人： ELLIOTT SAM
IPC分类号： G06F30/3323 , G06F30/3308
摘要： 하나이상의데이터변환요소를포함한데이터변환파이프라인용하드웨어설계를공식검증을통해검증하기위한방법및 시스템으로서, 하나이상의입력에대한데이터변환을수행하되, 공식검증은, 공식검증툴이수행해야하는데이터변환계산을단순화하는조건하에서수행된다. 일구현예에서, 데이터변환파이프라인사이에서실질적으로등가인데이터변환요소가동일한입력(들)에응답하여동일한출력(들)을생성하는제약하에서, 하드웨어설계의인스턴스의출력이소정의트랜잭션세트에대해다른데이터변환파이프라인용하드웨어설계의인스턴스와동일한출력을생성한다는것을공식적으로검증함으로써데이터변환파이프라인용하드웨어설계를검증한다.

4. 发明申请

WO2012120261A3 COMPRESSION OF A TESSELLATED PRIMITIVE INDEX LIST IN A TILE RENDERING SYSTEM 审中-公开
标题翻译：压缩系统中压缩的主要指标列表的压缩
公开(公告)号：WO2012120261A3
公开(公告)日：2013-04-25
申请号：PCT/GB2012000226
申请日：2012-03-08
申请人： IMAGINATION TECH LTD , FISHWICK STEVEN
发明人： FISHWICK STEVEN
IPC分类号： G06T9/00
CPC分类号： G06T17/20 , G06T9/001 , G06T9/004
摘要： A method and apparatus are provided for compressing a list of primitives in a computer graphics system from a tessellated patch of surface data. Uncompressed domain point indices (2410) are received and stored in an index buffer (2420). The domain point index for the next primitive in the list is compared (2430) with the domain point indices stored in the buffer to determine any matches. The domain point indices of the next primitive are stored in the buffer or, where a match was found, a reference to the position of the matched index. The step of storing the domain point indices in the buffer (2430) includes the storage of a further predicted domain point index which is computed from the domain point indices stored in the buffer. Compressed domain point indices (2490) for the tessellated patch are then output from the buffer. The domain point index value may split into a base identifier as an offset from that base position. The base identifier comprises a row number for point or line primitives or a ring/edge number for triangular primitives.
摘要翻译：提供了一种方法和装置，用于从表面数据的镶嵌补丁压缩计算机图形系统中的原语列表。未压缩域点索引（2410）被接收并存储在索引缓冲器（2420）中。将列表中下一个原语的域点索引与存储在缓冲区中的域点索引进行比较（2430）以确定任何匹配。下一个基元的域点索引存储在缓冲区中，或者在找到匹配项时，引用匹配索引的位置。将域点索引存储在缓冲器（2430）中的步骤包括从存储在缓冲器中的域点索引计算的另外预测的域点索引的存储。然后从缓冲区输出镶嵌补丁的压缩域点索引（2490）。域点索引值可能会分裂为与该基本位置的偏移量的基本标识符。基本标识符包括点或线原语的行号或三角形基元的环/边数。

5. 发明申请

WO2011114090A3 REQUESTS AND DATA HANDLING IN A BUS ARCHITECTURE 审中-公开
标题翻译：总线架构中的请求和数据处理
公开(公告)号：WO2011114090A3
公开(公告)日：2011-11-24
申请号：PCT/GB2011000291
申请日：2011-03-03
申请人： IMAGINATION TECH LTD , MEREDITH JASON
发明人： MEREDITH JASON
IPC分类号： G06F13/18 , G06F13/16
CPC分类号： G06F13/364 , G06F13/1621 , G06F13/1673
摘要： The present invention relates to improved methods for processing requests and sending data in a bus architecture. The present invention further relates to an improved bus architecture for processing requests and data. There is provided a method for processing read requests in a bus architecture comprising at least one master device connected to at least two slave devices via a bus. The architecture comprises an allocator for allocating incoming requests from the master device to a target slave device and an optimiser for each slave device. Each optimiser is for buffering incoming requests for the respective slave device. The method comprising the steps of: a) the master device sending a read request for a first slave device to the bus; b) the allocator generating a current-state indicator associated with the read request. The current-state indicator has an initial value, The method further comprises c) the allocator generating a priority indicator associated with the read request; d) the allocator sending the read request, the current-state indicator and the priority indicator to the optimiser of the first slave device; e) the optimiser of the first slave device receiving the read request, the current-state indicator and the priority indicator. Finally, if the initial value of the current-state indicator equals the value of the priority indicator, the method comprises processing the read request; or if the initial value of the current-state indicator does not equal the value of priority indicator, the method comprises deferring processing of the read request until a later time.
摘要翻译：本发明涉及用于在总线体系结构中处理请求和发送数据的改进方法。本发明还涉及用于处理请求和数据的改进的总线体系结构。提供了一种用于处理总线体系结构中的读请求的方法，该总线体系结构包括经由总线连接到至少两个从设备的至少一个主设备。该架构包括用于将来自主设备的传入请求分配给目标从设备的分配器以及用于每个从设备的优化器。每个优化器都用于缓存各个从设备的传入请求。该方法包括以下步骤：a）主设备发送对第一从设备的读请求到总线; b）分配器产生与读取请求相关联的当前状态指示符。当前状态指示符具有初始值。该方法还包括：c）分配器生成与读取请求相关联的优先级指示符; d）分配器将读取请求，当前状态指示符和优先级指示符发送给第一从设备的优化器; e）第一从设备的优化器接收读请求，当前状态指示符和优先级指示符。最后，如果当前状态指示符的初始值等于优先级指示符的值，则该方法包括处理读取请求; 或者如果当前状态指示符的初始值不等于优先级指示符的值，则该方法包括将读取请求的处理推迟到稍后的时间。

6. 发明申请

WO2010133833A3 A METHOD AND APPARATUS FOR RENDERING A COMPUTER GENERATED IMAGE 审中-公开
标题翻译：用于渲染计算机生成图像的方法和装置
公开(公告)号：WO2010133833A3
公开(公告)日：2011-03-03
申请号：PCT/GB2010000995
申请日：2010-05-17
申请人： IMAGINATION TECH LTD , FENNEY SIMON
发明人： FENNEY SIMON
IPC分类号： G06T15/00 , G06T17/20
CPC分类号： G06T17/20 , G06T15/005
摘要： A method and apparatus for rendering a computer generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. The method reduces the level of overdraw when rendering the arbitrary polygonal contour using a stencil buffer compared to other image space methods. A method of producing the primitives in an interleaved order, with second and higher level primitives being produced before the final first level primitives of the contour, is described which improves cache hit rate by reusing more vertices between primitives as they are produced.
摘要翻译：描述了使用模板缓冲器呈现计算机生成的图像的方法和装置。该方法将任意的闭合多边形轮廓划分成第一和更高级原语，其中第一级原语对应于任意封闭多边形轮廓中的连续顶点，并且较高级原语对应于紧接在前的原始级别的连续原语的结束顶点。与其他图像空间方法相比，使用模板缓冲区渲染任意多边形轮廓时，该方法可以降低覆盖水平。描述了以交错顺序产生原语的方法，其中在轮廓的最终第一级原语之前产生第二和更高级原语，其通过在产生原语之间重新使用多个顶点来改进高速缓存命中率。

7. 发明申请

WO2009133365A3 SCENE CHANGE DETECTION FOR RATE CONTROL 审中-公开
标题翻译：用于速率控制的场景变化检测
公开(公告)号：WO2009133365A3
公开(公告)日：2009-12-23
申请号：PCT/GB2009001085
申请日：2009-04-29
申请人： IMAGINATION TECH LTD , GAO JOHN , LEABACK PETER , HU MINGYOU
发明人： GAO JOHN , LEABACK PETER , HU MINGYOU
IPC分类号： H04N7/26
CPC分类号： H04N19/87 , H04N19/115 , H04N19/142 , H04N19/146 , H04N19/159 , H04N19/169
摘要： There is provided a method and apparatus for scene change detection for use with bit-rate control of a video compression system. The method and apparatus may be used for scene change detection in intra-coded and/or inter-coded pictures. The method comprises the steps of: compressing each picture in a video signal in turn; determining complexity data from the compressed signal for each picture after partial compression of the picture; determining from the complexity data whether a scene change may have taken place; and adjusting the compression step and allocated compressed bit number for pictures after a scene change detection in dependence on the result of the determination. For an intra-coded picture, the complexity data is a monotonically increasing function of a quantisation parameter and a compressed bit number used in the compression step for the partial compression from which the complexity data is determined. For an inter-coded picture, the complexity data is determined from a combination of a) the change of temporal prediction difference in relation to the average prediction difference of previous inter-coded pictures, b) the intra-coded macroblock number in the current inter-coded picture in relation to the average intra-coded macroblock number in previous inter-coded pictures, and c) the intra- coded macroblock number in the current inter-coded picture in relation to the total encoded macroblock number in the current inter-coded picture.
摘要翻译：提供了用于视频压缩系统的比特率控制的场景变化检测的方法和装置。该方法和装置可用于帧内编码和/或帧间编码图像中的场景变化检测。该方法包括以下步骤：依次压缩视频信号中的每个图像; 在图像的部分压缩之后从每个图像的压缩信号确定复杂度数据; 从复杂性数据确定场景变化是否可能发生; 并且根据确定结果调整压缩步骤并且在场景变化检测之后分配用于图像的压缩比特数。对于帧内编码图像，复杂度数据是量化参数和用于部分压缩的压缩步骤中使用的压缩比特数的单调递增函数，从该压缩步骤确定复杂度数据。对于帧间编码图像，复杂度数据由a）相对于先前帧间编码图像的平均预测差异的时间预测差的变化的组合确定，b）当前帧间编码的宏块数相关于先前帧间编码图像中的平均帧内编码宏块数的编码图像，以及c）当前帧间编码图像中当前帧间编码图像中的总编码宏块数目的帧内编码宏块数目图片。

8. 发明申请

WO2009133354A2 SYSTEM FOR PROVIDING TRACE DATA IN A DATA PROCESSOR HAVING A PIPELINED ARCHITECTURE 审中-公开
标题翻译：用于在具有管道结构的数据处理器中提供跟踪数据的系统
公开(公告)号：WO2009133354A2
公开(公告)日：2009-11-05
申请号：PCT/GB2009001070
申请日：2009-04-28
申请人： IMAGINATION TECH LTD , ISHERWOOD ROBERT GRAHAM , OLIVER IAN , WEBBER ANDREW
发明人： ISHERWOOD ROBERT GRAHAM , OLIVER IAN , WEBBER ANDREW
IPC分类号： G06F9/38
CPC分类号： G06F9/382 , G06F9/30076 , G06F9/3012 , G06F9/30145 , G06F9/3836 , G06F9/3842 , G06F9/3867 , G06F9/4881 , G06F11/3476 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions complete or not, providing trace information on the interrupt status of the processor, replacing instructions in the processor with functionally equivalent instructions that also produce trace information and modifying the scheduling of instructions in the processor based on the occupancy of a trace output buffer.
摘要翻译：本发明是一种用于在流水线数据处理器中提供跟踪数据的方法和系统。本发明的方面包括提供与执行流水线并行的跟踪流水线，提供关于条件指令是否完成的跟踪信息，提供关于处理器的中断状态的跟踪信息，用处理器中的指令替代功能上相同的指令，其也产生跟踪信息，并根据跟踪输出缓冲区的占用率修改处理器中指令的调度。

9. 发明申请

WO2007034232A3 SCALABLE MULTI-THREADED MEDIA PROCESSING ARCHITECTURE 审中-公开
标题翻译：可扩展多线程媒体处理架构
公开(公告)号：WO2007034232A3
公开(公告)日：2008-01-24
申请号：PCT/GB2006003603
申请日：2006-09-26
申请人： IMAGINATION TECH LTD , HOWSON JOHN
发明人： HOWSON JOHN
IPC分类号： G06F9/38 , G06F9/48 , G06F9/50
CPC分类号： G06F9/3851 , G06F9/3824 , G06F9/5011 , G06F2209/507
摘要： A method and apparatus are provided for processing multiple streams of data on a plurality of execution threads. Data is selected from a plurality of data sources (1001 ). An address in the data storage means (1036) is allocated for the data thus selected. The selected data is then loaded into the allocated address. Following this an execution task comprising the selected data source, the data address and an execution address is constructed and the data task is queued with previously constructed tasks. A determination is made as to which processing resources are required for each task and tasks are selected for execution in dependence on this. Tasks selected for execution are distributed across a plurality of processing threads (170). The allocation of data storage in the data storage means includes the steps of selecting data from one of the data sources and supplying a code execution address to a programmable data sequencer (1004). The code from the code execution address is executed to cause data to be written to the data storage means. Furthermore, a tile based computer graphic rendering system may comprise a plurality of mulit-threaded processor cores. Each processor core is allocated to different sectors of the tile.
摘要翻译：提供了一种用于在多个执行线程上处理多个数据流的方法和装置。从多个数据源（1001）中选择数据。为这样选择的数据分配数据存储装置（1036）中的地址。然后将选定的数据加载到分配的地址中。在此之后，包括所选数据源的执行任务，构建数据地址和执行地址，并且数据任务与先前构造的任务排队。确定每个任务需要哪些处理资源，并根据此选择执行任务。选择执行的任务分布在多个处理线程（170）上。数据存储装置中的数据存储的分配包括从数据源之一中选择数据并将代码执行地址提供给可编程数据定序器（1004）的步骤。执行代码执行地址的代码以使数据被写入数据存储装置。此外，基于瓦片的计算机图形呈现系统可以包括多个多线程处理器核心。每个处理器核心分配给瓦片的不同扇区。

10. 发明申请

WO2007052044A3 MOTION ESTIMATION USING MOTION BLUR INFORMATION 审中-公开
标题翻译：使用运动信息的运动估计
公开(公告)号：WO2007052044A3
公开(公告)日：2007-07-12
申请号：PCT/GB2006004112
申请日：2006-11-02
申请人： IMAGINATION TECH LTD , HEYWARD SIMON NICHOLAS
发明人： HEYWARD SIMON NICHOLAS
IPC分类号： H04N7/26 , G06T7/20
CPC分类号： H04N7/50 , G06T7/223 , H04N5/145 , H04N19/14 , H04N19/176 , H04N19/182 , H04N19/51 , H04N19/513 , H04N19/521 , H04N19/61
摘要： A method and apparatus are provided for estimating motion in a sequence of video images. A plurality of fields of a sequence of video images are stored; then for each of a plurality of blocks of pixels in each field a test is performed on a set of candidate motion vectors to determinate which motion vector gives the best benefit in determining the motion between adjacent fields for that block. The testing step includes determining the amount of motion blur present in the image and modifying the testing of candidate motion vectors in dependence on this motion blur.
摘要翻译：提供了一种用于估计视频图像序列中的运动的方法和装置。存储一系列视频图像的多个场; 那么对于每个场中的多个像素块中的每一个，对一组候选运动矢量执行测试，以确定哪个运动矢量在确定该块的相邻场之间的运动方面给出最好的益处。测试步骤包括确定图像中存在的运动模糊量，并根据该运动模糊修改候选运动矢量的测试。

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