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    • 4. 发明授权
    • Memory core and semiconductor memory device having the same
    • 存储器芯和半导体存储器件具有相同的功能
    • US08050071B2
    • 2011-11-01
    • US12980975
    • 2010-12-29
    • Je-Min YuIn-Chul Jeong
    • Je-Min YuIn-Chul Jeong
    • G11C5/02
    • G11C11/4085G11C8/08G11C8/14
    • A memory core capable of decreasing the area of core conjunction region is disclosed. The memory core includes a first sub word-line driving circuit and a first sub word-line control signal generating circuit. The first sub word-line driving circuit is disposed in a first region, and generates a first word-line driving signal to provide the first word-line driving signal to an array unit. The first sub word-line control signal generating circuit is disposed in the first region, and generates the first sub word-line control signal based on a sub word-line driving signal. Therefore, the memory core has a small size and, consequently so can the semiconductor device.
    • 公开了一种能够减小芯连接区域面积的记忆体。 存储器芯包括第一副字线驱动电路和第一副字线控制信号发生电路。 第一子字线驱动电路设置在第一区域中,并产生第一字线驱动信号,以将第一字线驱动信号提供给阵列单元。 第一副字线控制信号发生电路设置在第一区域中,并且基于子字线驱动信号产生第一副字线控制信号。 因此,存储器芯具有小的尺寸,因此半导体器件也是如此。
    • 6. 发明申请
    • Frequency measuring circuit and semiconductor device having the same
    • 频率测量电路和具有该频率测量电路的半导体器件
    • US20100237918A1
    • 2010-09-23
    • US12661668
    • 2010-03-22
    • In-Chul Jeong
    • In-Chul Jeong
    • H03L7/06
    • H03K5/133G11C19/00G11C19/28H03L7/0812
    • A frequency measuring circuit and a semiconductor device having the frequency measuring circuit include a divided and shifted clock signal generator, a delayed clock signal generator and a phase detecting unit. The divided and shifted clock signal generator divides a frequency of a clock signal input from an exterior to output a frequency-divided clock signal, and delays the frequency-divided clock signal by a time proportional to a period of the clock signal to output a shifted clock signal. The delayed clock signal generator delays the frequency-divided clock signal by a fixed time to generate a plurality of delayed clock signals. The phase detecting unit receives the plurality of delayed clock signals and the shifted clock signal and detects a phase difference between each of the plurality of delayed clock signals and the shifted clock signal to output a plurality of phase detecting signals that represent information related to a frequency of the clock signal
    • 具有频率测量电路的频率测量电路和半导体器件包括分频移位时钟信号发生器,延迟时钟信号发生器和相位检测单元。 分频移位时钟信号发生器分频从外部输入的时钟信号的频率,以输出分频时钟信号,并将分频时钟信号延迟与时钟信号周期成比例的时间,以输出偏移 时钟信号。 延迟时钟信号发生器将分频时钟信号延迟固定时间以产生多个延迟的时钟信号。 相位检测单元接收多个延迟的时钟信号和移位的时钟信号,并且检测多个延迟时钟信号中的每一个与移位的时钟信号之间的相位差,以输出表示与频率有关的信息的多个相位检测信号 的时钟信号