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1. 发明授权

US09292288B2 Systems and methods for flag tracking in move elimination operations 有权
标题翻译：移动消除操作中标志跟踪的系统和方法
公开(公告)号：US09292288B2
公开(公告)日：2016-03-22
申请号：US13861009
申请日：2013-04-11
申请人： Vijaykumar B. Kadgi , Jeremy R. Anderson , James D. Hadley , Tong Li , Matthew C. Merten
发明人： Vijaykumar B. Kadgi , Jeremy R. Anderson , James D. Hadley , Tong Li , Matthew C. Merten
IPC分类号： G06F9/30 , G06F9/45 , G06F9/38
CPC分类号： G06F9/30105 , G06F8/443 , G06F9/30032 , G06F9/30094 , G06F9/30098 , G06F9/3013 , G06F9/30181 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.
摘要翻译：涉及移动消除的数据处理操作中标志跟踪的系统和方法。示例性处理系统包括包括多个物理寄存器值的第一数据结构; 第二数据结构，包括引用第一数据结构的元素的多个指针; 包括多个移动消除集合的第三数据结构，每个移动消除集合包括表示两个或多个逻辑数据寄存器的两个或多个位，所述第三数据结构还包括与每个移动消除集相关联的至少一个位，所述至少一个位表示一个或多个逻辑标志寄存器; 第四数据结构，包括与标志寄存器共享第一数据结构的元素的数据寄存器的标识符; 以及配置为执行移动消除操作的移动消除逻辑。

2. 发明申请

US20140310504A1 Systems and Methods for Flag Tracking in Move Elimination Operations 有权
标题翻译：移动消除操作中标志跟踪的系统和方法
公开(公告)号：US20140310504A1
公开(公告)日：2014-10-16
申请号：US13861009
申请日：2013-04-11
申请人： VIJAYKUMAR B. KADGI , JEREMY R. ANDERSON , JAMES D. HADLEY , TONG LI , MATTHEW C. MERTEN
发明人： VIJAYKUMAR B. KADGI , JEREMY R. ANDERSON , JAMES D. HADLEY , TONG LI , MATTHEW C. MERTEN
IPC分类号： G06F9/30
CPC分类号： G06F9/30105 , G06F8/443 , G06F9/30032 , G06F9/30094 , G06F9/30098 , G06F9/3013 , G06F9/30181 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.
摘要翻译：涉及移动消除的数据处理操作中标志跟踪的系统和方法。示例性处理系统包括包括多个物理寄存器值的第一数据结构; 第二数据结构，包括引用第一数据结构的元素的多个指针; 包括多个移动消除集合的第三数据结构，每个移动消除集合包括表示两个或多个逻辑数据寄存器的两个或多个位，所述第三数据结构还包括与每个移动消除集相关联的至少一个位，所述至少一个位表示一个或多个逻辑标志寄存器; 第四数据结构，包括与标志寄存器共享第一数据结构的元素的数据寄存器的标识符; 以及配置为执行移动消除操作的移动消除逻辑。

3. 发明授权

US10235180B2 Scheduler implementing dependency matrix having restricted entries 有权
公开(公告)号：US10235180B2
公开(公告)日：2019-03-19
申请号：US13723684
申请日：2012-12-21
申请人： Srikanth T. Srinivasan , Matthew C. Merten , Bambang Sutanto , Rahul R. Kulkarni , Justin M. Deinlein , James D. Hadley
发明人： Srikanth T. Srinivasan , Matthew C. Merten , Bambang Sutanto , Rahul R. Kulkarni , Justin M. Deinlein , James D. Hadley
IPC分类号： G06F9/30 , G06F9/38
摘要： A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction.

4. 发明申请

US20140095838A1 Physical Reference List for Tracking Physical Register Sharing 有权
标题翻译：用于跟踪物理寄存器共享的物理参考列表
公开(公告)号：US20140095838A1
公开(公告)日：2014-04-03
申请号：US13631664
申请日：2012-09-28
申请人： VIJAYKUMAR VIJAY KADGI , JAMES D. HADLEY , AVINASH SODANI , MATTHEW C. MERTEN , MORRIS MARDEN , JOSEPH A. MCMAHON , GRACE C. LEE , LAURA A. KNAUTH , ROBERT S. CHAPPELL , FARIBORZ TABESH
发明人： VIJAYKUMAR VIJAY KADGI , JAMES D. HADLEY , AVINASH SODANI , MATTHEW C. MERTEN , MORRIS MARDEN , JOSEPH A. MCMAHON , GRACE C. LEE , LAURA A. KNAUTH , ROBERT S. CHAPPELL , FARIBORZ TABESH
IPC分类号： G06F9/30
CPC分类号： G06F9/30105 , G06F9/384
摘要： A processor includes a processing unit including a storage module having stored thereon a physical reference list for storing identifications of physical registers that have been referenced by multiple logical registers, and a reclamation module for reclaiming physical registers to a free list based on a count of each of the physical registers on the physical reference list.
摘要翻译：处理器包括处理单元，该处理单元包括存储有存储有多个逻辑寄存器所引用的物理寄存器的标识的物理参考列表的存储模块，以及用于基于每个的物理寄存器在物理参考列表中。

5. 发明授权

US06931516B2 Pipelined instruction decoder for multi-threaded processors 失效
标题翻译：多线程处理器的流水线指令解码器
公开(公告)号：US06931516B2
公开(公告)日：2005-08-16
申请号：US10615918
申请日：2003-07-08
申请人： Jonathan P. Douglas , Daniel J. Deleganes , James D. Hadley
发明人： Jonathan P. Douglas , Daniel J. Deleganes , James D. Hadley
IPC分类号： G06F9/38
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3808 , G06F9/3851 , G06F9/3861 , G06F9/3867
摘要： A pipelined instruction decoder for a multithread processor including an instruction decode pipeline, a valid bit pipeline, and a thread identification pipeline in parallel together, with each having the same predetermined number of pipe stages. The instruction decode pipeline to decode instructions associated with a plurality of instruction threads. The valid bit pipeline to associate a valid indicator at each pipe stage with each instruction being decoded in the instruction decode pipeline. The thread identification pipeline to associate a thread-identification at each pipestage with each instruction being decoded in the instruction decode pipeline. The pipelined instruction decoder may further include a pipeline controller to control the clocking of each pipe stage of the instruction decode pipeline, the valid bit pipeline, and the thread identification pipeline. The pipeline controller may invalidate an entire thread of instructions, squeeze out invalid instructions, and/or conserve power by selectively stopping the clocking of pipestages.
摘要翻译：一种用于多线程处理器的流水线指令解码器，包括指令解码流水线，有效位流水线和并行在一起的线程识别流水线，每个流水线指令解码器具有相同的预定数量的管道级。该指令解码流水线解码与多条指令线程相关联的指令。有效位流水线将每个管道阶段的有效指示器与指令解码流水线中的每个指令进行解码。线程识别流水线，用于将每个分支处的线程标识与在指令解码流水线中解码的每条指令相关联。流水线指令解码器还可以包括流水线控制器，以控制指令解码流水线，有效位流水线和线程识别流水线的每个管段的时钟。流水线控制器可以通过选择性地停止分支的时钟来使整个指令线程无效，挤出无效指令和/或节省功率。

6. 发明授权

US06609193B1 Method and apparatus for multi-thread pipelined instruction decoder 失效
标题翻译：多线程流水线指令解码器的方法和装置
公开(公告)号：US06609193B1
公开(公告)日：2003-08-19
申请号：US09475105
申请日：1999-12-30
申请人： Jonathan P. Douglas , Daniel J. Deleganes , James D. Hadley
发明人： Jonathan P. Douglas , Daniel J. Deleganes , James D. Hadley
IPC分类号： G06F938
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3808 , G06F9/3851 , G06F9/3861 , G06F9/3867
摘要： A multithread pipelined instruction decoder to clock, clear and stall an instruction decode pipeline of a multi-threaded machine to maximize performance and minimize power. A shadow pipeline shadows the instruction decode pipeline maintaining a the thread-identification and instruction-valid bits for each pipestage of the instruction decoder. The thread-id and valid bits are used to control the clear, clock, and stall of each pipestage of the instruction decoder. Instructions of one thread can be cleared without impacting instructions of another thread in the decode pipeline. In some cases, instructions of one thread can be stalled without impacting instructions of another thread in the decode pipeline. In the present invention, pipestages are clocked only when a valid instruction needs to advance in order to conserve power and to minimize stalling.
摘要翻译：多线程流水线指令解码器，用于对多线程机器的指令解码流水线进行时钟，清除和停止，以最大限度地提高性能并最大限度地降低功耗。阴影管线阴影指示解码管道，维护指令解码器的每个管道的线程标识和指令有效位。线程ID和有效位用于控制指令解码器的每个分支的清除，时钟和失速。可以清除一个线程的指令，而不影响解码流水线中另一个线程的指令。在某些情况下，一个线程的指令可以停止，而不影响解码流水线中另一个线程的指令。在本发明中，仅当有效指令需要提前才能节省功率并使失速最小化时，才能对分支管进行计时。

7. 发明申请

US20140181476A1 Scheduler Implementing Dependency Matrix Having Restricted Entries 审中-公开
标题翻译：调度器实现具有限制条目的依赖矩阵
公开(公告)号：US20140181476A1
公开(公告)日：2014-06-26
申请号：US13723684
申请日：2012-12-21
申请人： Srikanth T. Srinivasan , Matthew C. Merten , Bambang Sutanto , Rahul R. Kulkarni , Justin M. Deinlein , James D. Hadley
发明人： Srikanth T. Srinivasan , Matthew C. Merten , Bambang Sutanto , Rahul R. Kulkarni , Justin M. Deinlein , James D. Hadley
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction.
摘要翻译：公开了实现具有限制条目的依赖矩阵的调度器。本公开的处理装置包括：解码单元，用于对指令进行解码;以及可通信地耦合到解码单元的调度器。在一个实施例中，调度器被配置为接收解码的指令，确定解码的指令限定为由调度器维护的依赖矩阵中的受限保留站（RS）条目类型的分配，识别依赖矩阵中的RS条目将所识别的空闲RS条目中的一个分配给依赖矩阵中的解码指令的信息，并且通过解码指令的源依赖性信息更新与所要求的RS条目相对应的依赖矩阵的一行。

8. 发明申请

US20140095814A1 Memory Renaming Mechanism in Microarchitecture 审中-公开
标题翻译：微体系结构中的内存重命名机制
公开(公告)号：US20140095814A1
公开(公告)日：2014-04-03
申请号：US13631644
申请日：2012-09-28
申请人： MORRIS MARDEN , VIJAYKUMAR VIJAY KADGI , JAMES D. HADLEY , MATTHEW C. MERTEN , GRACE C. LEE , JOSEPH A. MCMAHON , ROBERT S. CHAPPELL , LAURA A. KNAUTH , FARIBORZ TABESH
发明人： MORRIS MARDEN , VIJAYKUMAR VIJAY KADGI , JAMES D. HADLEY , MATTHEW C. MERTEN , GRACE C. LEE , JOSEPH A. MCMAHON , ROBERT S. CHAPPELL , LAURA A. KNAUTH , FARIBORZ TABESH
IPC分类号： G06F12/00
CPC分类号： G06F9/384 , G06F9/30043
摘要： A processor includes a processing unit including a storage module having stored thereon a table for tracking physical registers in which each store operation stores source data and a memory renaming module for register renaming load operations based on the table.
摘要翻译：处理器包括处理单元，该处理单元包括存储模块，存储模块用于跟踪物理寄存器，其中每个存储操作存储源数据，以及用于基于该表进行寄存器重命名加载操作的存储器重命名模块。

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