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1. 发明申请

US20090042363A1 Method for manufacturing bonded wafer and outer-peripheral grinding machine of bonded wafer 有权
标题翻译：接合晶片的制造方法以及接合晶片的外周磨削机的制造方法
公开(公告)号：US20090042363A1
公开(公告)日：2009-02-12
申请号：US11920761
申请日：2006-05-18
申请人： Susumu Miyazaki , Tokio Takei , Keiichi Okabe
发明人： Susumu Miyazaki , Tokio Takei , Keiichi Okabe
IPC分类号： H01L21/30 , B24B5/00
CPC分类号： H01L21/304 , H01L21/2007 , H01L21/76256
摘要： The present invention provides a method for manufacturing a bonded wafer, which includes at least the steps of bonding a bond wafer and a base wafer, grinding an outer peripheral portion of the bonded bond wafer, etching off an unbonded portion of the ground bond wafer, and then reducing a thickness of the bond wafer, wherein, in the step of grinding the outer peripheral portion, the bonded bond wafer is ground so as to form a groove along the outer peripheral portion of the bond wafer to form an outer edge portion outside the groove; and in the subsequent step of etching, the outer edge portion is removed together with the groove portion of the bond wafer to form a terrace portion where the base wafer is exposed at the outer peripheral portion of the bonded wafer. Thus, it is possible to provide a method for manufacturing a bonded wafer, which can reduce the number of dimples formed in a terrace portion of a base wafer upon removing an outer peripheral portion of a bonded bond wafer.
摘要翻译：本发明提供一种接合晶片的制造方法，其至少包括接合晶片和基底晶片的接合步骤，研磨接合接合晶片的外周部分，蚀刻接地晶片的未结合部分，然后减小接合晶片的厚度，其中，在研磨外周部分的步骤中，接合的接合晶片被研磨以沿着接合晶片的外周部分形成凹槽以形成外部边缘部分凹槽并且在随后的蚀刻步骤中，外边缘部分与接合晶片的沟槽部分一起被去除，以形成露台部分，其中基底晶片在接合晶片的外周部分露出。因此，可以提供一种用于制造接合晶片的方法，其可以在去除接合的接合晶片的外周部分时减少形成在基底晶片的台阶部分中的凹坑的数量。

2. 发明申请

US20080166823A1 Method for Evaluating Semiconductor Wafer, Apparatus for Evaluating Semiconductor Wafer, and Method for Manufacturing Semiconductor Wafer 有权
标题翻译：用于评估半导体晶片的方法，用于评估半导体晶片的装置以及半导体晶片的制造方法
公开(公告)号：US20080166823A1
公开(公告)日：2008-07-10
申请号：US11886266
申请日：2006-03-24
申请人： Keiichi Okabe , Hisakazu Takano , Daisuke Nakamata
发明人： Keiichi Okabe , Hisakazu Takano , Daisuke Nakamata
IPC分类号： G01B7/28 , H01L21/66
CPC分类号： G01B7/281 , G01Q30/04 , G01Q60/363 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for evaluating nanotopography of a surface of a semiconductor wafer sliced from a semiconductor ingot, the method being conducted prior to polishing of the surface, the method at least comprising: measuring a surface profile of the wafer in the direction that the wafer is sliced; determining a maximum inclination value of warp change of the wafer surface in a sectional profile in the direction that the wafer is sliced of the measured surface profile; and estimating nanotopography of the wafer surface after being polished based on the determined maximum value. As a result, there are provided a method and an apparatus for evaluating nanotopography of a surface of a semiconductor wafer, and a method for manufacturing a semiconductor wafer exhibiting good nanotopography level on the surface.
摘要翻译：本发明提供了一种用于评估从半导体晶片切片的半导体晶片的表面的纳米形貌的方法，所述方法在抛光表面之前进行，该方法至少包括：测量晶片的表面轮廓，将晶片切片; 确定在所述晶片被切割的所述测量的表面轮廓的方向上的所述晶片表面的翘曲变化的最大倾斜度值; 以及基于所确定的最大值来估计抛光后的晶片表面的纳米形貌。结果，提供了一种用于评估半导体晶片的表面的纳米形貌的方法和装置，以及用于制造在表面上具有良好的纳米形貌水平的半导体晶片的方法。

3. 发明授权

US06220928B1 Surface grinding method and apparatus for thin plate work 失效
标题翻译：薄板加工的表面研磨方法及装置
公开(公告)号：US06220928B1
公开(公告)日：2001-04-24
申请号：US09301348
申请日：1999-04-29
申请人： Keiichi Okabe , Hisashi Oshima , Sadayuki Okuni , Tadahiro Kato
发明人： Keiichi Okabe , Hisashi Oshima , Sadayuki Okuni , Tadahiro Kato
IPC分类号： B24B4900
CPC分类号： B24B7/228 , B24B49/00 , B24B51/00
摘要： The present invention provides a surface grinding method and apparatus for achieving a thin plate work such as a semiconductor wafer with high flatness, high accuracy and certainty and the apparatus comprises: a surface grinder in which a grinding wheel support member 3 by which a rotary shaft 5 of a grinding wheel 6 is supported is held by a pivotal shaft portion 4 and a grinding wheel shaft inclination control motor 9 which displaces the grinding wheel support member 3 by activating the pivotal shaft portion 4 is provided; a corrective angle storage device 15 which stores a corrective angle of an inclination angle of a rotary shaft 5 of the grinding wheel 6 to a rotary shaft 13 of a wafer 12; and a shaft inclination control apparatus 14 which sends out a signal to control the grinding wheel shaft inclination control motor 9 while reading a corrective angle of the corrective angle storage device 15, wherein a relative inclination angle of the grinding wheel to the thin plate work, in a more concrete manner an inclination angle of the rotary shaft 5 of the grinding wheel 6, is changed for each of grinding steps of high rate feed, low rate feed and spark-out.
摘要翻译：本发明提供了一种用于实现诸如半导体晶片的薄平板工作的平面磨削方法和装置，其具有高平坦度，高精度和确定性，并且该装置包括：平面磨床，其中砂轮支撑构件3通过旋转轴砂轮6的支承体5由转轴部4保持，砂轮轴倾斜控制马达9通过使枢轴部4动作来移动砂轮支承部件3。修正角度存储装置15，其将研磨轮6的旋转轴5的倾斜角度的修正角度存储到晶片12的旋转轴13; 以及轴倾斜控制装置14，其在读取矫正角度存储装置15的校正角度的同时发出信号以控制砂轮轴倾斜控制电动机9，其中，砂轮与薄板的相对倾斜角度作用，更具体地说，对于高速率进给，低速率进给和火花塞的每个研磨步骤，改变了砂轮6的旋转轴5的倾斜角度。

4. 发明申请

US20090233109A1 Method for Producing Bonded Wafer, Bonded Wafer, and Surface Grinding Machine 审中-公开
标题翻译：粘结晶片，粘结晶片和平面磨床的生产方法
公开(公告)号：US20090233109A1
公开(公告)日：2009-09-17
申请号：US11886877
申请日：2006-03-29
申请人： Keiichi Okabe , Yoshikazu Tachikawa , Susumu Miyazaki , Sigeyuki Yoshizawa , Tokio Takei
发明人： Keiichi Okabe , Yoshikazu Tachikawa , Susumu Miyazaki , Sigeyuki Yoshizawa , Tokio Takei
IPC分类号： B24B49/04 , H01L21/66 , B24B49/12 , B32B9/00
CPC分类号： B24B7/228 , B24B49/12 , H01L21/3212 , H01L21/76256 , H01L22/26 , Y10T428/31663
摘要： The present invention is a method for producing a bonded wafer, comprising at least: bonding a base wafer serving as a support substrate to a bond wafer made of a silicon single crystal via an insulator film or directly bonding the wafers to provide a bonded wafer; and reducing a thickness of the bond wafer to form a thin film made of the silicon single crystal on the base wafer, wherein the thickness of the bonded wafer is reduced based on at least surface grinding while measuring the thickness of the bond wafer, and surface grinding with respect to the bond wafer is stopped when the thickness of the bond wafer reaches a target thickness. As a result, the method for producing a bonded wafer enabling a silicon single crystal thin film to precisely have a desired film thickness, a bonded wafer, and a surface grinding machine enabling a silicon single crystal thin film to precisely have a desired film thickness are provided.
摘要翻译：本发明是一种用于制造接合晶片的方法，至少包括：通过绝缘膜将用作支撑衬底的基底晶片接合到由硅单晶制成的接合晶片上，或直接接合晶片以提供接合晶片; 并且减小接合晶片的厚度以在基底晶片上形成由单晶硅制成的薄膜，其中，至少基于表面研磨减少接合晶片的厚度，同时测量接合晶片的厚度和表面当接合晶片的厚度达到目标厚度时，停止对接合晶片的研磨。结果，能够使硅单晶薄膜精确地具有期望的膜厚的接合晶片的制造方法，接合晶片和能够使硅单晶薄膜精确地具有期望的膜厚度的表面研磨机，提供。

5. 发明申请

US20090111245A1 Method for manufacturing bonded wafer 有权
标题翻译：贴合晶圆的制造方法
公开(公告)号：US20090111245A1
公开(公告)日：2009-04-30
申请号：US11921081
申请日：2006-05-18
申请人： Keiichi Okabe , Susumu Miyazaki
发明人： Keiichi Okabe , Susumu Miyazaki
IPC分类号： H01L21/302 , H01L21/02
CPC分类号： H01L21/76256
摘要： The present invention provides a method for manufacturing a bonded wafer comprising steps of forming an oxide film on at least a surface of a base wafer or a surface of a bond wafer; bringing the base wafer and the bond wafer into close contact via the oxide film; subjecting these wafers to a heat treatment under an oxidizing atmosphere to bond the wafers together; grinding and removing the outer periphery of the bond wafer so that the outer periphery has a predetermined thickness; subsequently removing an unbonded portion of the outer periphery of the bond wafer by etching; and then thinning the bond wafer so that the bond wafer has a desired thickness, wherein the etching is conducted by using a mixed acid at 30° C. or less at least comprising hydrofluoric acid, nitric acid, and acetic acid. Thus there is provided a method for manufacturing a bonded wafer by which unbonded portions of the outer periphery of the bond wafer are removed with a high selectivity ratio (RSi/RSiO2) without causing metallic contamination.
摘要翻译：本发明提供了一种用于制造接合晶片的方法，包括以下步骤：在基底晶片或接合晶片的表面的至少一个表面上形成氧化膜; 使基底晶片和接合晶片经由氧化膜紧密接触; 在氧化气氛下对这些晶片进行热处理以将晶片粘合在一起; 研磨和去除接合晶片的外周，使得外周具有预定厚度; 随后通过蚀刻去除接合晶片的外周的未结合部分; 然后使接合晶片变薄，使得接合晶片具有期望的厚度，其中通过使用至少包含氢氟酸，硝酸和乙酸的30℃或更低的混合酸来进行蚀刻。因此，提供了一种制造接合晶片的方法，通过该方法，以高选择率（RSi / RSiO2）除去接合晶片的外周的未结合部分而不引起金属污染。

6. 发明授权

US06284658B1 Manufacturing process for semiconductor wafer 失效
标题翻译：半导体晶圆制造工艺
公开(公告)号：US06284658B1
公开(公告)日：2001-09-04
申请号：US09348276
申请日：1999-07-07
申请人： Tadahiro Kato , Sadayuki Okuni , Keiichi Okabe , Hisashi Oshima
发明人： Tadahiro Kato , Sadayuki Okuni , Keiichi Okabe , Hisashi Oshima
IPC分类号： H01L21302
CPC分类号： H01L21/02008
摘要： The present invention has an object to provide a manufacturing process of a semiconductor wafer in which improvement on accuracy in a chamfering portion is realized. The manufacturing process of a semiconductor wafer comprises: a slicing step of obtaining a wafer in the shaped of a thin disk by slicing a single crystal ingot; a surface-grinding step of flattening a surface of the wafer; a chamfering step of chamfering the peripheral edge portions; and mirror-polishing step of mirror-polishing the surface of the wafer, wherein a simultaneous double-side surface-grinding step of grinding both sides of the wafer simultaneously by a double-side grinding machine is existent prior to the chamfering step in order to remove wafer waviness and a secondary grinding step is performed by grinding a single side or simultaneously both sides of the wafer after the chamfering step is carried out, so that improvement on accuracy in a chamfered portion is realized.
摘要翻译：本发明的目的是提供一种半导体晶片的制造工艺，其中实现了倒角部分精度的提高。半导体晶片的制造工艺包括：切片步骤，通过切片单晶锭获得薄盘状的晶片; 表面研磨步骤，使晶片的表面变平; 倒角步骤，对所述周缘部进行倒角; 以及镜面抛光晶片的表面的镜面抛光步骤，其中在倒角步骤之前存在同时双面研磨步骤，其通过双面研磨机同时研磨晶片的两侧，以便在通过在进行倒角步骤之后研磨晶片的单面或同时进行二次研磨步骤，从而实现倒角部分精度的提高。

7. 发明授权

US09093498B2 Method for manufacturing bonded wafer 有权
公开(公告)号：US09093498B2
公开(公告)日：2015-07-28
申请号：US11921081
申请日：2006-05-18
申请人： Keiichi Okabe , Susumu Miyazaki
发明人： Keiichi Okabe , Susumu Miyazaki
IPC分类号： H01L21/762
CPC分类号： H01L21/76256
摘要： The present invention provides a method for manufacturing a bonded wafer comprising steps of forming an oxide film on at least a surface of a base wafer or a surface of a bond wafer; bringing the base wafer and the bond wafer into close contact via the oxide film; subjecting these wafers to a heat treatment under an oxidizing atmosphere to bond the wafers together; grinding and removing the outer periphery of the bond wafer so that the outer periphery has a predetermined thickness; subsequently removing an unbonded portion of the outer periphery of the bond wafer by etching; and then thinning the bond wafer so that the bond wafer has a desired thickness, wherein the etching is conducted by using a mixed acid at 30° C. or less at least comprising hydrofluoric acid, nitric acid, and acetic acid. Thus there is provided a method for manufacturing a bonded wafer by which unbonded portions of the outer periphery of the bond wafer are removed with a high selectivity ratio (RSi/RSiO2) without causing metallic contamination.

8. 外观设计

USD584355S1 Electronic pen 有权
标题翻译：电子笔
公开(公告)号：USD584355S1
公开(公告)日：2009-01-06
申请号：US29297394
申请日：2007-11-09
申请人： Masataka Hidaka , Yukinobu Kudo , Keiichi Okabe
设计人： Masataka Hidaka , Yukinobu Kudo , Keiichi Okabe

9. 发明授权

US07810383B2 Method for evaluating semiconductor wafer, apparatus for evaluating semiconductor wafer, and method for manufacturing semiconductor wafer 有权
标题翻译：半导体晶片的评价方法，半导体晶片的评价装置及半导体晶片的制造方法
公开(公告)号：US07810383B2
公开(公告)日：2010-10-12
申请号：US11886266
申请日：2006-03-24
申请人： Keiichi Okabe , Hisakazu Takano , Daisuke Nakamata
发明人： Keiichi Okabe , Hisakazu Takano , Daisuke Nakamata
IPC分类号： G01B5/28
CPC分类号： G01B7/281 , G01Q30/04 , G01Q60/363 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for evaluating nanotopography of a surface of a semiconductor wafer sliced from a semiconductor ingot, the method being conducted prior to polishing of the surface, the method at least comprising: measuring a surface profile of the wafer in the direction that the wafer is sliced; determining a maximum inclination value of warp change of the wafer surface in a sectional profile in the direction that the wafer is sliced of the measured surface profile; and estimating nanotopography of the wafer surface after being polished based on the determined maximum value. As a result, there are provided a method and an apparatus for evaluating nanotopography of a surface of a semiconductor wafer, and a method for manufacturing a semiconductor wafer exhibiting good nanotopography level on the surface.
摘要翻译：本发明提供了一种用于评估从半导体晶片切片的半导体晶片的表面的纳米形貌的方法，所述方法在抛光表面之前进行，该方法至少包括：测量晶片的表面轮廓，将晶片切片; 确定在所述晶片被切割的所述测量的表面轮廓的方向上的所述晶片表面的翘曲变化的最大倾斜度值; 以及基于所确定的最大值来估计抛光后的晶片表面的纳米形貌。结果，提供了一种用于评估半导体晶片的表面的纳米形貌的方法和装置，以及用于制造在表面上具有良好的纳米形貌水平的半导体晶片的方法。

10. 发明授权

US06583029B2 Production method for silicon wafer and SOI wafer, and SOI wafer 有权
标题翻译：硅晶片和SOI晶片以及SOI晶圆的生产方法
公开(公告)号：US06583029B2
公开(公告)日：2003-06-24
申请号：US09926645
申请日：2001-11-28
申请人： Takao Abe , Tokio Takei , Keiichi Okabe , Hajime Miyajima
发明人： Takao Abe , Tokio Takei , Keiichi Okabe , Hajime Miyajima
IPC分类号： H01L2130
CPC分类号： H01L21/02021 , B24B9/065 , B24B37/042 , H01L21/76254 , Y10S438/906
摘要： There are provided a method for manufacturing a mirror polished wafer with little polishing sag (peripheral sag) by a relatively easy method, a method for manufacturing a bonded wafer having an SOI layer or a bond layer which has no periphery removing region or reduces it, and a bonded wafer thereof. There is prepared a silicon wafer having chamfered portions in which when the chamfering width of the front surface side of the silicon wafer is X1 and the chamfering width of the back surface side thereof is X2, X1 X1).
摘要翻译：提供了一种通过相对容易的方法制造具有很少抛光凹陷（外围凹陷）的镜面抛光晶片的方法，制造具有SOI层或不具有外围去除区域或者减少它的接合层的接合晶片的方法，和其接合晶片。制备具有倒角部分的硅晶片，其中当硅晶片的正面侧的倒角宽度为X1，并且其背面侧的倒角宽度为X2时，X1 X1）。

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