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1. 发明授权

US09142767B2 Resistive memory cell including integrated select device and storage element 有权
标题翻译：电阻式存储单元包括集成选择器件和存储元件
公开(公告)号：US09142767B2
公开(公告)日：2015-09-22
申请号：US13234875
申请日：2011-09-16
申请人： David H. Wells , D. V. Nirmal Ramaswamy , Kirk D. Prall
发明人： David H. Wells , D. V. Nirmal Ramaswamy , Kirk D. Prall
IPC分类号： H01L47/00 , H01L45/00 , H01L27/24
CPC分类号： H01L45/085 , G11C2213/73 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/146
摘要： Resistive memory cells including an integrated select device and storage element and methods of forming the same are described herein. As an example, a resistive memory cell can include a select device structure including a Schottky interface, and a storage element integrated with the select device structure such that an electrode corresponding to the Schottky interface serves as a first electrode of the storage element. The storage element can include a storage material formed between the first electrode and a second electrode.
摘要翻译：包括集成选择装置和存储元件的电阻式存储单元及其形成方法在此描述。作为示例，电阻式存储单元可以包括包括肖特基接口的选择器件结构和与选择器件结构集成的存储元件，使得对应于肖特基界面的电极用作存储元件的第一电极。存储元件可以包括形成在第一电极和第二电极之间的存储材料。

2. 发明授权

US08441056B2 NROM memory cell, memory array, related devices and methods 有权
公开(公告)号：US08441056B2
公开(公告)日：2013-05-14
申请号：US12795906
申请日：2010-06-08
申请人： Kirk D. Prall , Leonard Forbes
发明人： Kirk D. Prall , Leonard Forbes
IPC分类号： H01L29/72
CPC分类号： H01L27/11568 , G11C11/5692 , G11C16/0475 , H01L27/115
摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

3. 发明申请

US20130088909A1 CROSS-POINT MEMORY COMPENSATION 有权
公开(公告)号：US20130088909A1
公开(公告)日：2013-04-11
申请号：US13269717
申请日：2011-10-10
申请人： Zengtao T. Liu , Kirk D. Prall
发明人： Zengtao T. Liu , Kirk D. Prall
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/004 , G11C8/08 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/0033 , G11C13/0038 , G11C2013/0054 , G11C2013/0057 , G11C2013/0083 , G11C2213/77
摘要： The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

4. 发明授权

US08351242B2 Electronic devices, memory devices and memory arrays 有权
公开(公告)号：US08351242B2
公开(公告)日：2013-01-08
申请号：US12893992
申请日：2010-09-29
申请人： D. V. Nirmal Ramaswamy , Kirk D. Prall
发明人： D. V. Nirmal Ramaswamy , Kirk D. Prall
IPC分类号： G11C11/00 , G11C11/34 , H01L27/105
CPC分类号： H01L45/14 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146
摘要： Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells.

5. 发明授权

US08268692B2 Non-volatile memory cell devices and methods 有权
标题翻译：非易失性存储单元器件及方法
公开(公告)号：US08268692B2
公开(公告)日：2012-09-18
申请号：US13154618
申请日：2011-06-07
申请人： Gurtej S. Sandhu , Kirk D. Prall
发明人： Gurtej S. Sandhu , Kirk D. Prall
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332
摘要： A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.
摘要翻译：一种制造存储单元的方法，包括在第一介电层上形成纳米点并在纳米点上形成隔间电介质层，其中隔间电介质层封装在纳米点上。为了形成存储器单元的侧壁，隔离介电层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对栅极间电介质层选择性的蚀刻来去除间隔栅电介质层和纳米点的剩余部分。

6. 发明授权

US08063436B2 Memory cells configured to allow for erasure by enhanced F-N tunneling of holes from a control gate to a charge trapping material 有权
标题翻译：存储单元被配置为允许通过增强的F-N隧穿从控制门到电荷捕获材料的擦除来擦除
公开(公告)号：US08063436B2
公开(公告)日：2011-11-22
申请号：US12829904
申请日：2010-07-02
申请人： Arup Bhattacharyya , Kirk D. Prall , Luan C. Tran
发明人： Arup Bhattacharyya , Kirk D. Prall , Luan C. Tran
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0433 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/115 , H01L29/513
摘要： Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling of holes from the control gate to the charge trapping material.
摘要翻译：存储单元包括控制栅极，电荷捕获材料和控制栅极与电荷捕获材料之间的电荷阻挡材料。电荷阻挡材料被配置为允许通过从控制栅极到电荷捕获材料的孔的增强的F-N隧穿来擦除存储器单元。

7. 发明申请

US20110233641A1 NON-VOLATILE MEMORY CELL DEVICES AND METHODS 有权
标题翻译：非易失性存储器单元和方法
公开(公告)号：US20110233641A1
公开(公告)日：2011-09-29
申请号：US13154618
申请日：2011-06-07
申请人： Gurtej S. Sandhu , Kirk D. Prall
发明人： Gurtej S. Sandhu , Kirk D. Prall
IPC分类号： H01L29/788 , B82Y99/00
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332
摘要： A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.
摘要翻译：一种制造存储单元的方法，包括在第一介电层上形成纳米点并在纳米点上形成隔间电介质层，其中隔间电介质层封装在纳米点上。为了形成存储器单元的侧壁，隔离介电层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对栅极间电介质层选择性的蚀刻来去除间隔栅电介质层和纳米点的剩余部分。

8. 发明申请

US20100244117A1 NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS 有权
标题翻译： NROM存储单元，存储阵列，相关设备和方法
公开(公告)号：US20100244117A1
公开(公告)日：2010-09-30
申请号：US12795906
申请日：2010-06-08
申请人： Kirk D. Prall , Leonard Forbes
发明人： Kirk D. Prall , Leonard Forbes
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , G11C11/5692 , G11C16/0475 , H01L27/115
摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.
摘要翻译：配置为存储每个F2的至少一个位的存储器单元的阵列包括基本上垂直的结构，提供间隔距离等于阵列的最小间距的一半的距离的电子存储器功能。提供电子存储器功能的结构被配置为存储每个门多于一个位。阵列还包括到存储器单元的电接触，包括基本垂直的结构。电池可以被编程为具有与栅极绝缘体相邻的多个电荷水平中的一个，其邻近于第一源极/漏极区域，使得沟道区域具有第一电压阈值区域（Vt1）和第二电压阈值区域（Vt2）并且使得编程单元以降低的漏极源电流工作。

9. 发明授权

US07541242B2 NROM memory cell, memory array, related devices and methods 有权
标题翻译： NROM存储单元，存储器阵列，相关器件和方法
公开(公告)号：US07541242B2
公开(公告)日：2009-06-02
申请号：US11346413
申请日：2006-02-02
申请人： Kirk D. Prall , Leonard Forbes
发明人： Kirk D. Prall , Leonard Forbes
IPC分类号： H01L21/332
CPC分类号： H01L29/7926 , G11C11/5692 , G11C16/0466 , G11C16/0475 , H01L27/11556 , H01L27/11582 , H01L29/7889 , H01L29/7923
摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.
摘要翻译：配置为存储每个F2的至少一个位的存储器单元的阵列包括基本上垂直的结构，提供间隔距离等于阵列的最小间距的一半的距离的电子存储器功能。提供电子存储器功能的结构被配置为存储每个门多于一个位。阵列还包括到存储器单元的电接触，包括基本垂直的结构。电池可以被编程为具有与栅极绝缘体相邻的多个电荷水平中的一个，其邻近于第一源极/漏极区域，使得沟道区域具有第一电压阈值区域（Vt1）和第二电压阈值区域（Vt2）并且使得编程单元以降低的漏极源电流工作。

10. 发明授权

US07535048B2 NROM memory cell, memory array, related devices and methods 有权
公开(公告)号：US07535048B2
公开(公告)日：2009-05-19
申请号：US11346049
申请日：2006-02-02
申请人： Kirk D. Prall , Leonard Forbes
发明人： Kirk D. Prall , Leonard Forbes
IPC分类号： H01L27/108
CPC分类号： H01L29/7926 , G11C11/5692 , G11C16/0466 , G11C16/0475 , H01L27/11556 , H01L27/11582 , H01L29/7889 , H01L29/7923
摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

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