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1. 发明授权

US08435848B2 PMOS SiGe-last integration process 有权
标题翻译： PMOS SiGe最后一个整合过程
公开(公告)号：US08435848B2
公开(公告)日：2013-05-07
申请号：US13283817
申请日：2011-10-28
申请人： Manoj Mehrotra
发明人： Manoj Mehrotra
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A process of forming a CMOS integrated circuit including integrating SiGe source/drains in the PMOS transistor after source/drain and LDD implants and anneals. A dual layer hard mask is formed on a polysilicon gate layer. The bottom layer prevents SiGe growth on the polysilicon gate. The top layer protects the bottom layer during source/drain spacer removal. A stress memorization layer may be formed on the integrated circuit prior to a source/drain anneal and removed prior to forming a SiGe blocking layer over the NMOS. SiGe spacers may be formed on the PMOS gate to laterally offset the SiGe recesses.
摘要翻译：一种形成CMOS集成电路的过程，包括在源极/漏极和LDD注入和退火之后在PMOS晶体管中集成SiGe源极/漏极。双层硬掩模形成在多晶硅栅极层上。底层可防止多晶硅栅极上的SiGe生长。顶层在源/排水间隔物移除期间保护底层。在源极/漏极退火之前，可以在集成电路上形成应力记忆层，并且在NMOS上形成SiGe阻挡层之前被去除。 SiGe间隔物可以形成在PMOS栅极上以横向偏移SiGe凹部。

2. 发明申请

US20120108021A1 PMOS SiGe-LAST INTEGRATION PROCESS 有权
标题翻译： PMOS SiGe-LAST整合过程
公开(公告)号：US20120108021A1
公开(公告)日：2012-05-03
申请号：US13283817
申请日：2011-10-28
申请人： Manoj Mehrotra
发明人： Manoj Mehrotra
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A process of forming a CMOS integrated circuit including integrating SiGe source/drains in the PMOS transistor after source/drain and LDD implants and anneals. A dual layer hard mask is formed on a polysilicon gate layer. The bottom layer prevents SiGe growth on the polysilicon gate. The top layer protects the bottom layer during source/drain spacer removal. A stress memorization layer may be formed on the integrated circuit prior to a source/drain anneal and removed prior to forming a SiGe blocking layer over the NMOS. SiGe spacers may be formed on the PMOS gate to laterally offset the SiGe recesses.
摘要翻译：一种形成CMOS集成电路的过程，包括在源极/漏极和LDD注入和退火之后在PMOS晶体管中集成SiGe源极/漏极。在多晶硅栅极层上形成双层硬掩模。底层可防止多晶硅栅极上的SiGe生长。顶层在源/排水间隔物移除期间保护底层。在源极/漏极退火之前，可以在集成电路上形成应力记忆层，并且在NMOS上形成SiGe阻挡层之前被去除。 SiGe间隔物可以形成在PMOS栅极上以横向偏移SiGe凹部。

3. 发明申请

US20100164003A1 MULTIPLE INDIUM IMPLANT METHODS AND DEVICES AND INTEGRATED CIRCUITS THEREFROM 有权
标题翻译：多种植入式植入方法及装置及集成电路
公开(公告)号：US20100164003A1
公开(公告)日：2010-07-01
申请号：US12344843
申请日：2008-12-29
申请人： PUNEET KOHLI , MANOJ MEHROTRA
发明人： PUNEET KOHLI , MANOJ MEHROTRA
IPC分类号： H01L27/088 , H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26513 , H01L21/823412 , H01L29/1083 , H01L29/66507 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region are on opposing sides of the gate stack. An In region having a retrograde profile is under at least a portion of the channel region. The retrograde profile includes (i) a surface In concentration at a semiconductor surface interface with the gate dielectric of less than 5×1016 cm−3, (ii) a peak In concentration at least 20 nm from the semiconductor surface below the gate dielectric, and wherein (iii) the peak In concentration is at least two (2) orders of magnitude higher than the In concentration at the semiconductor surface interface. A method to form an IC including at least one NMOS transistor includes implanting a first In implant at a first energy and a second In implant at a second energy, wherein the first In implant together with the second In implant form an In region having a retrograde profile under at least a portion of the channel region, and wherein the second energy is at least 5 keV more than the first energy.
摘要翻译：集成电路（IC）包括至少一个NMOS晶体管，其中NMOS晶体管包括具有半导体表面的衬底，以及形成在栅极电介质上的包括栅电极的表面中或其上的栅堆叠，其中沟道区域位于在栅极电介质下方的半导体表面。源极和漏极区域在栅极堆叠的相对侧上。具有逆行轮廓的An In区域在通道区域的至少一部分的下方。逆行曲线包括（i）与栅极电介质的半导体表面界面处的表面In浓度小于5×10 16 cm -3，（ii）从栅极电介质下方的半导体表面至少20nm的峰In浓度，并且其中（iii）峰In浓度比半导体表面界面处的In浓度高至少两（2）个数量级。一种形成包括至少一个NMOS晶体管的IC的方法，包括以第二能量以第一能量和第二In的植入物注入第一InNo，其中第一In植入物与第二In植入物一起形成具有逆行的In区域在所述通道区域的至少一部分下形成，并且其中所述第二能量比所述第一能量多至少5keV。

4. 发明授权

US07736983B2 High threshold NMOS source-drain formation with As, P and C to reduce damage 有权
标题翻译：具有As，P和C的高阈值NMOS源极 - 漏极形成，以减少损伤
公开(公告)号：US07736983B2
公开(公告)日：2010-06-15
申请号：US11972417
申请日：2008-01-10
申请人： Puneet Kohli , Manoj Mehrotra , Shaoping Tang
发明人： Puneet Kohli , Manoj Mehrotra , Shaoping Tang
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26586 , H01L21/823418 , H01L29/0847 , H01L29/6659 , H01L29/7833
摘要： Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implantation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1·1014 cm−2 arsenic in the NSD and a high threshold NMOS transistor formed with the inventive method are also disclosed.
摘要翻译： n型轻掺杂漏极（NLDD）区域和n型源极/漏极（NDS）区域的管道缺陷与砷植入相关，而NLDD和NSD区域的过度扩散主要是由于磷间质运动。碳注入通常用于减少NLDD中的磷扩散，但有助于栅极二极管泄漏（GDL）。在高阈值NMOS晶体管中，GDL通常是主要的截止状态泄漏机制。本发明提供了一种形成NMOS晶体管的方法，其中没有碳注入到NLDD中，并且NSD由前非晶化植入物（PAI），磷植入物和碳种植入物形成。在NDS中使用碳可以提供更高浓度的磷，从而降低串联电阻并减少管道缺陷。还公开了在NSD中具有小于1×1014cm-2砷的NMOS晶体管和由本发明方法形成的高阈值NMOS晶体管。

5. 发明申请

US20100112764A1 Use of Poly Resistor Implant to Dope Poly Gates 有权
标题翻译：使用聚电阻植入物涂覆聚合物门
公开(公告)号：US20100112764A1
公开(公告)日：2010-05-06
申请号：US12265358
申请日：2008-11-05
申请人： Manoj Mehrotra , Puneet Kohli
发明人： Manoj Mehrotra , Puneet Kohli
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L27/0629
摘要： A process of fabricating an IC is disclosed in which a polysilicon resistor and a gate region of an MOS transistor are implanted concurrently. The concurrent implantation may be used to reduce steps in the fabrication sequence of the IC. The concurrent implantation may also be used to provide another species of transistor in the IC with enhanced performance. Narrow PMOS transistor gates may be implanted concurrently with p-type polysilicon resistors to increase on-state drive current. PMOS transistor gates over thick gate dielectrics may be implanted concurrently with p-type polysilicon resistors to reduce gate depletion. NMOS transistor gates may be implanted concurrently with n-type polysilicon resistors to reduce gate depletion, and may be implanted concurrently with p-type polysilicon resistors to provide high threshold NMOS transistors in the IC.
摘要翻译：公开了一种制造IC的工艺，其中同时注入多晶硅电阻器和MOS晶体管的栅极区域。同时植入可用于减少IC制造顺序中的步骤。同时植入也可用于在IC中提供另一种具有增强性能的晶体管。可以与p型多晶硅电阻同时注入窄PMOS晶体管栅极，以增加导通状态驱动电流。厚栅极电介质上的PMOS晶体管栅极可以与p型多晶硅电阻同时注入，以减少栅极耗尽。 NMOS晶体管栅极可以与n型多晶硅电阻同时注入以减少栅极耗尽，并且可以与p型多晶硅电阻同时注入，以在IC中提供高阈值NMOS晶体管。

6. 发明申请

US20090127620A1 SEMICONDUCTOR DOPING WITH REDUCED GATE EDGE DIODE LEAKAGE 有权
标题翻译：具有降低栅极边缘二极管漏电的半导体器件
公开(公告)号：US20090127620A1
公开(公告)日：2009-05-21
申请号：US11941129
申请日：2007-11-16
申请人： Puneet Kohli , Nandakumar Mahalingam , Manoj Mehrotra , Song Zhao
发明人： Puneet Kohli , Nandakumar Mahalingam , Manoj Mehrotra , Song Zhao
IPC分类号： H01L23/00 , H01L21/425
CPC分类号： H01L21/26513 , H01L21/26506 , H01L29/165 , H01L29/6659 , H01L29/7833
摘要： Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and drain extension region dopant profiles without significantly inducing gate edge diode leakage. The technique follows the discovery that carbon, which may be used as a diffusion suppressant for dopants such as boron, may produce a gate edge diode leakage if present in significant quantities in the source and drain extension regions. As an alternative to placing carbon in the source and drain extension regions, carbon may be placed in the source and drain regions, and the thermal anneal used to activate the dopant may be relied upon to diffuse a small concentration of the carbon into the source and drain extension regions, thereby suppressing dopant diffusion in these regions without significantly inducing gate edge diode leakage. The increased concentration of carbon in the source and drain regions may permit heavier doping of the source/drain region, leading to improved gate capacitance.
摘要翻译：公开了半导体掺杂技术以及相关方法和结构，其产生具有更紧密控制的源极和漏极延伸区掺杂物分布而不显着引起栅极边缘二极管泄漏的元件。该技术遵循发现，可以用作掺杂剂如硼的扩散抑制剂的碳可能在源极和漏极延伸区域中以大量存在而产生栅极边缘二极管泄漏。作为在源极和漏极延伸区域中放置碳的替代方案，可以将碳放置在源极和漏极区域中，并且可以依靠用于激活掺杂剂的热退火将碳的少量浓度扩散到源中，漏极延伸区域，从而抑制这些区域中的掺杂剂扩散，而不会显着引起栅极边缘二极管泄漏。源极和漏极区域中增加的碳浓度可能允许源极/漏极区域的较重掺杂，导致改善的栅极电容。

7. 发明申请

US20090004803A1 MULTI-STAGE IMPLANT TO IMPROVE DEVICE CHARACTERISTICS 有权
标题翻译：多阶段植入物提高装置特性
公开(公告)号：US20090004803A1
公开(公告)日：2009-01-01
申请号：US11769058
申请日：2007-06-27
申请人： Manoj Mehrotra , Stan Ashburn , Shaoping Tang
发明人： Manoj Mehrotra , Stan Ashburn , Shaoping Tang
IPC分类号： G11C11/34 , H01L21/8238
CPC分类号： G11C11/412 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L27/11 , H01L27/1104 , H01L29/1083 , H01L29/7833
摘要： One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are formed that are associated with the gate structure. After forming the implanted source and drain regions, a multi-stage implant is performed on the source and drain regions that comprises at least two implants where the dose and energy of the first implant varies from the dose and energy of the second implant. Other methods and devices are also disclosed.
摘要翻译：本发明人的概念的一个方面涉及形成半导体器件的方法。在该方法中，在半导体本体上形成栅极结构。源极/漏极掩模在半导体本体注入源上形成图案，并且形成与栅极结构相关联的漏极区。在形成植入的源区和漏区之后，在包括至少两个植入物的源极和漏极区域上执行多级注入，其中第一注入的剂量和能量与第二植入物的剂量和能量不同。还公开了其它方法和装置。

8. 发明申请

US20080318387A1 Activation of CMOS Source/Drain Extensions by Ultra-High Temperature Anneals 有权
标题翻译：通过超高温退火激活CMOS源极/漏极扩展
公开(公告)号：US20080318387A1
公开(公告)日：2008-12-25
申请号：US11764980
申请日：2007-06-19
申请人： Amitabh Jain , Manoj Mehrotra
发明人： Amitabh Jain , Manoj Mehrotra
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/2255 , H01L21/268 , H01L21/2686 , H01L21/823814 , H01L29/6659
摘要： A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底上形成栅极电介质层。在栅极电介质层上形成栅电极。将掺杂剂注入到衬底的延伸区域中，其中掺杂剂的量保留在与栅电极相邻的电介质层中。衬底在约1000℃或更高的温度下进行退火，以使掺杂剂的量的至少一部分扩散到半导体衬底中。

9. 发明申请

US20080268628A1 N-TYPE SEMICONDUCTOR COMPONENT WITH IMPROVED DOPANT IMPLANTATION PROFILE AND METHOD OF FORMING SAME 审中-公开
标题翻译：具有改进的嫁接轮廓的N型半导体元件及其形成方法
公开(公告)号：US20080268628A1
公开(公告)日：2008-10-30
申请号：US11739965
申请日：2007-04-25
申请人： Puneet Kohli , Manoj Mehrotra , Antonio Luis Pacheco Rotondaro , Stan Ashburn , Nandakumar Mahalingam , Amitabh Jain
发明人： Puneet Kohli , Manoj Mehrotra , Antonio Luis Pacheco Rotondaro , Stan Ashburn , Nandakumar Mahalingam , Amitabh Jain
IPC分类号： H01L21/425 , H01L29/00 , H01L21/22
CPC分类号： H01L21/26513 , H01L21/26506 , H01L29/66575
摘要： The disclosure relates to a method of forming an n-type doped active area on a semiconductor substrate that presents an improved placement profile. The method comprises the placement of arsenic in the presence of a carbon-containing arsenic diffusion suppressant in order to reduce the diffusion of the arsenic out of the target area during heat-induced annealing. The method may additionally include the placement of an amorphizer, such as germanium, in the target area in order to reduce channeling of the arsenic ions through the crystalline lattice. The method may also include the use of arsenic in addition to another n-type dopant, e.g. phosphorus, in order to offset some of the disadvantages of a pure arsenic dopant. The disclosure also relates to a semiconductor component, e.g. an NMOS transistor, formed in accordance with the described methods.
摘要翻译：本公开涉及一种在半导体衬底上形成n型掺杂有源区的方法，该方法具有改善的放置曲线。该方法包括在含碳的砷扩散抑制剂的存在下放置砷，以便在热诱导退火期间减少砷扩散到目标区域之外。该方法可以另外包括在目标区域中放置诸如锗的非晶硅化合物，以便减少砷离子通过晶格的通道。该方法还可以包括除了另一种n型掺杂剂之外使用砷，例如，磷，以便抵消纯砷掺杂剂的一些缺点。本公开还涉及半导体部件，例如，一个根据所述方法形成的NMOS晶体管。

10. 发明授权

US07344929B2 Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity 有权
标题翻译：使用具有反射率的封盖层制造集成电路的方法
公开(公告)号：US07344929B2
公开(公告)日：2008-03-18
申请号：US11034791
申请日：2005-01-13
申请人： Manoj Mehrotra , Amitabh Jain
发明人： Manoj Mehrotra , Amitabh Jain
IPC分类号： H01L21/00
CPC分类号： H01L21/324 , H01L21/823814 , H01L21/823871 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer (210) over a transistor device having source/drain regions (150, 155) located over a substrate (110), the capping layer (210) having a degree of reflectivity, and annealing the transistor device through the capping layer (210) using photons (310), the annealing of the transistor device affected by the degree of reflectivity.
摘要翻译：本发明提供一种制造半导体器件的方法和集成电路的制造方法。除了其他步骤之外，制造半导体器件的方法包括在具有位于衬底（110）上方的源/漏区（150,155）的晶体管器件上形成覆盖层（210），所述覆盖层（210）具有并且通过使用光子（310）的覆盖层（210）退火晶体管器件，晶体管器件的退火受到反射率的影响。

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