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1. 发明申请

US20200218669A1 APPARATUSES, SYSTEMS, AND METHODS FOR INVALIDATING EXPIRED MEMORY 审中-公开
公开(公告)号：US20200218669A1
公开(公告)日：2020-07-09
申请号：US16820630
申请日：2020-03-16
申请人： Ginger H. Gilsdorf , Karthik Kumar , Mark A. Schmisseur , Thomas Willhalm , Francesc Guim Bernat
发明人： Ginger H. Gilsdorf , Karthik Kumar , Mark A. Schmisseur , Thomas Willhalm , Francesc Guim Bernat
IPC分类号： G06F12/123 , G06F12/0891 , G06F12/02 , G06F1/14 , G11C7/22
摘要： An apparatus and/or system is described including a memory device including a memory range and a temporal data management unit (TDMU) coupled to the memory device to receive from an interface, the memory range and a temporal range corresponding to validity of data in the memory range, check the temporal range against a time and/or date value provided by a timer or clock to identify the data in the memory range as expired, and invalidate the data that is expired in the memory device. In some embodiments, the TDMU includes hardware logic that resides on a memory module with the memory device and is coupled to invalidate expired data when the memory module is decoupled from the interface. Other embodiments may be disclosed and claimed.

2. 发明授权

US07596652B2 Integrated circuit having processor and bridging capabilities 失效
标题翻译：集成电路具有处理器和桥接功能
公开(公告)号：US07596652B2
公开(公告)日：2009-09-29
申请号：US10846459
申请日：2004-05-14
申请人： Mark A. Schmisseur , Deif N. Atallah
发明人： Mark A. Schmisseur , Deif N. Atallah
IPC分类号： G06F13/36
CPC分类号： G06F13/4027
摘要： An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a processor, a bridge, and circuitry capable of coupling the bridge and the processor to a first bus and to a second bus. The first bus may be compatible with a first bus protocol, the second bus may be compatible with a second bus protocol, and the first and second bus protocols may be different from each other. The bridge may be capable of, in response at least in part to a request from the processor, preventing a command received at the bridge via the first bus from being forwarded from the bridge to the second bus. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：根据一个实施例的装置可以包括集成电路。集成电路可以包括处理器，桥接器和能够将桥接器和处理器耦合到第一总线和第二总线的电路。第一总线可以与第一总线协议兼容，第二总线可以与第二总线协议兼容，并且第一和第二总线协议可以彼此不同。至少部分地响应于来自处理器的请求，桥可以能够阻止经由第一总线在桥接处接收的命令从桥接器转发到第二总线。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

3. 发明授权

US07197605B2 Allocating cache lines 有权
标题翻译：分配缓存行
公开(公告)号：US07197605B2
公开(公告)日：2007-03-27
申请号：US10335204
申请日：2002-12-30
申请人： Mark A. Schmisseur , Brett W. Gaines
发明人： Mark A. Schmisseur , Brett W. Gaines
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0886 , G06F12/127
摘要： Allocating cache lines includes incurring a cache write miss and, after incurring the cache write miss, writing data having a memory address to a cache line that does not include data at the memory address and that includes only invalid data.
摘要翻译：分配高速缓存线包括引起高速缓存写入未命中，并且在引起高速缓存写入未命中之后，将具有存储器地址的数据写入不包括存储器地址上的数据并且仅包括无效数据的高速缓存行。

4. 发明授权

US6128718A Apparatus and method for a base address register on a computer peripheral device supporting configuration and testing of address space size 失效
标题翻译：支持配置和测试地址空间大小的计算机外围设备上的基地址寄存器的装置和方法
公开(公告)号：US6128718A
公开(公告)日：2000-10-03
申请号：US919376
申请日：1997-08-28
申请人： Mark A. Schmisseur , Barry Davis
发明人： Mark A. Schmisseur , Barry Davis
IPC分类号： G06F9/30 , G06F9/355 , G06F9/35 , G06F12/10
CPC分类号： G06F9/342
摘要： A method for providing a base address register in a computer system that allows the length of the base address portion of an address to be changed and thereby allows various sizes of address spaces to be supported by the same base address register. The method employs steps that enable and disable bits of the base address register to properly support the desired address space size. Some embodiments of the method set disabled bits of the base address register to a known value. An apparatus that employs the method includes a second register connected to the base address register to supply signals that enable and disable bits of the base address register appropriately.
摘要翻译：一种用于在计算机系统中提供基地址寄存器的方法，其允许改变地址的基址部分的长度，从而允许相同基址寄存器支持各种大小的地址空间。该方法采用启用和禁用基地址寄存器的位以适当地支持所需地址空间大小的步骤。该方法的一些实施例将基址寄存器的禁用位设置为已知值。采用该方法的装置包括连接到基地址寄存器的第二寄存器，以适当地提供启用和禁用基地址寄存器的位的信号。

5. 发明申请

US20130305006A1 METHOD, SYSTEM AND APPARATUS FOR REGION ACCESS CONTROL 有权
标题翻译：方法，用于区域访问控制的系统和设备
公开(公告)号：US20130305006A1
公开(公告)日：2013-11-14
申请号：US13997504
申请日：2011-09-30
申请人： Asher M. Altman , Mark A. Schmisseur , Robert C. Swanson , Thomas M. Slaight
发明人： Asher M. Altman , Mark A. Schmisseur , Robert C. Swanson , Thomas M. Slaight
IPC分类号： G06F12/14
CPC分类号： G06F12/14 , G06F3/0622 , G06F3/0667 , G06F3/0679 , G06F9/545 , G06F21/6281
摘要： Techniques and mechanisms for providing access to a storage device of a computer platform. In an embodiment, an agent executing on the platform may be registered for access to the storage device, the agent being allocated a memory space by a host operating system of the platform. Registration of the agent may result in a location in the allocated memory space being mapped to a location in the storage device. In another embodiment, the agent may write to the location in the allocated memory space to request access to the storage device, wherein the request is independent of any system call to the host OS which describes the requested access.
摘要翻译：用于提供对计算机平台的存储设备的访问的技术和机制。在一个实施例中，可以登记在平台上执行的代理以访问存储设备，代理由平台的主机操作系统分配存储器空间。代理的注册可能导致分配的存储器空间中的位置被映射到存储设备中的位置。在另一个实施例中，代理可以写入分配的存储器空间中的位置以请求对存储设备的访问，其中该请求独立于描述所请求的访问的对主机OS的任何系统调用。

6. 发明授权

US07464199B2 Method, system, and program for handling Input/Output commands 有权
标题翻译：用于处理输入/输出命令的方法，系统和程序
公开(公告)号：US07464199B2
公开(公告)日：2008-12-09
申请号：US11279086
申请日：2006-04-07
申请人： Sailesh Bissessur , Richard P. Mackey , Mark A. Schmisseur , David R. Smith
发明人： Sailesh Bissessur , Richard P. Mackey , Mark A. Schmisseur , David R. Smith
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.
摘要翻译：提供了一种用于处理输入/输出（I / O）请求的方法，系统和程序。总线使得能够与发起者，目标设备和设备控制器进行通信，其中设备控制器访问目标设备以执行指向目标设备的I / O命令。接收到I / O请求命令以访问目标设备。启动器被配置为将总线上的至少一个数据请求发送到设备控制器的预定义地址窗口中的一个存储器地址。设备控制器被允许从总线上的启动器向预定义的地址窗口中的存储器地址提出数据请求，以针对目标设备执行数据请求。

7. 发明申请

US20210318965A1 PLATFORM DATA AGING FOR ADAPTIVE MEMORY SCALING 有权
公开(公告)号：US20210318965A1
公开(公告)日：2021-10-14
申请号：US17357662
申请日：2021-06-24
申请人： Karthik Kumar , Francesc Guim Bernat , Mark A Schmisseur
发明人： Karthik Kumar , Francesc Guim Bernat , Mark A Schmisseur
IPC分类号： G06F12/123 , G06F12/14 , G06F12/02 , G06F1/3234
摘要： The platform data aging for adaptive memory scaling described herein provides technical solutions for technical problems facing power management for electronic device processors. Technical solutions described herein include improved processor power management based on a memory region life-cycle (e.g., short-lived, long-lived, static). In an example, a short-term memory request is allocated to a short-term memory region, and that short-term memory region is powered down upon expiration of the lifetime of all short-term memory requests on the short-term memory region. Multiple memory regions may be scaled down (e.g., shut down) or scaled up based on demands for memory capacity and bandwidth.

8. 发明申请

US20140181365A1 Techniques to Configure a Solid State Drive to Operate in a Storage Mode or a Memory Mode 有权
标题翻译：配置固态硬盘在存储模式或内存模式下运行的技术
公开(公告)号：US20140181365A1
公开(公告)日：2014-06-26
申请号：US13725502
申请日：2012-12-21
申请人： BLAISE FANNING , MARK A. SCHMISSEUR , RAYMOND S. TETRICK , ROBERT J. ROYER, JR. , DAVID B. MINTURN , SHANE MATTHEWS
发明人： BLAISE FANNING , MARK A. SCHMISSEUR , RAYMOND S. TETRICK , ROBERT J. ROYER, JR. , DAVID B. MINTURN , SHANE MATTHEWS
IPC分类号： G06F12/02
CPC分类号： G06F3/0604 , G06F3/0629 , G06F3/0632 , G06F3/0634 , G06F3/0644 , G06F3/0664 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F13/16 , G06F13/28 , G06F2212/7206
摘要： Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.
摘要翻译：公开了用于配置固态驱动器（SSD）以在存储模式或存储器模式下操作的示例。在一些示例中，可以在具有一个或多个非易失性存储器阵列的SSD的控制器处接收一个或多个配置命令。 SSD可以被配置为基于一个或多个配置命令以存储模式，存储模式或者存储模式或存储器模式的组合中的至少一个进行操作。其他的例子被描述和要求保护。

9. 发明申请

US20140006696A1 APPARATUS AND METHOD FOR PHASE CHANGE MEMORY DRIFT MANAGEMENT 有权
标题翻译：相位变化管理的设备和方法
公开(公告)号：US20140006696A1
公开(公告)日：2014-01-02
申请号：US13994116
申请日：2011-12-20
申请人： Raj K. Ramanujan , Mark A. Schmisseur
发明人： Raj K. Ramanujan , Mark A. Schmisseur
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/214 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C16/3418 , G11C2013/0054 , G11C2013/0057
摘要： A system and method are described for selecting a demarcation voltage for read and write operations. Embodiments of the invention provide a scheme to use multiple VDMs to cover the case where power-on drift is different from power-off drift of the PCMS cells. The controller automatically manages this through tracking refreshes and writes. In addition, the embodiments of the invention provide an efficient scheme to reduce the performance impact of the penalty box following a write by tracking recent write addresses through a hash-table or similar scheme. By way of example, a method in accordance with one embodiment comprises: detecting a read operation directed to a first block of a PCMS memory; determining whether a write operation has previously occurred to the first block within a specified amount of time prior to the read operation; using a first demarcation voltage (VDM) for the read operation if the write operation has previously occurred to the first block within the specified amount of time prior to the write operation; and using a second VDM for the read operation if the write operation has not previously occurred to the first block within the specified amount of time prior to the write or refresh operation.
摘要翻译：描述了用于选择用于读取和写入操作的分界电压的系统和方法。本发明的实施例提供了使用多个VDM来覆盖上电漂移与PCMS单元的断电漂移不同的情况的方案。控制器通过跟踪刷新和写入自动进行管理。此外，本发明的实施例提供了一种有效的方案，以通过通过散列表或类似方案跟踪最近的写入地址来减少写入之后的惩罚盒的性能影响。作为示例，根据一个实施例的方法包括：检测针对PCMS存储器的第一块的读取操作; 在所述读取操作之前的指定时间内确定是否先前对所述第一块发生了写入操作; 如果在写操作之前的指定时间内先前已经对第一块发生写操作，则使用第一分界电压（VDM）作为读操作; 以及如果在所述写入或刷新操作之前的所述指定时间量内的所述第一块以前没有发生写入操作，则使用第二VDM进行所述读取操作。

10. 发明授权

US07290127B2 System and method of remotely initializing a local processor 失效
标题翻译：远程初始化本地处理器的系统和方法
公开(公告)号：US07290127B2
公开(公告)日：2007-10-30
申请号：US10032762
申请日：2001-12-26
申请人： Mark A Schmisseur , Timothy J Jehl , Richard P Mackey , Delf Atallah
发明人： Mark A Schmisseur , Timothy J Jehl , Richard P Mackey , Delf Atallah
IPC分类号： G06F15/177
CPC分类号： G06F1/24
摘要： A system and method of initializing a core processing circuit are disclosed. The core processing circuit is held in a reset state while a reset vector is loaded to one or more registers at a boot address associated with the core processing circuit. The reset vector is loaded from a system memory through a host bridge. The reset vector comprises one or more instructions to initialize the core processing system upon release from a reset state.
摘要翻译：公开了一种初始化核心处理电路的系统和方法。核心处理电路被保持在复位状态，而复位向量被加载到与核心处理电路相关联的引导地址的一个或多个寄存器。复位向量通过主机桥从系统存储器加载。复位向量包括在从复位状态释放时初始化核心处理系统的一个或多个指令。

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