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1. 发明授权

US09312260B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US09312260B2
公开(公告)日：2016-04-12
申请号：US13086186
申请日：2011-04-13
申请人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
发明人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
IPC分类号： H01L29/76 , H01L27/092 , H01L21/8238 , H01L23/485 , H01L27/02 , H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L27/092 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L29/0649 , H01L29/4238 , H01L29/495 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域分离。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属结构与第一源区电耦合。第二金属结构与第二漏区电耦合。第三金属结构设置在第一和第二金属结构之上并与第一和第二金属结构电耦合。第一金属结构体的宽度基本上等于或大于第三金属结构体的宽度。

2. 发明申请

US20130094035A1 MULTIPLE PATTERNING TECHNOLOGY METHOD AND SYSTEM FOR ACHIEVING MINIMAL PATTERN MISMATCH 有权
标题翻译：用于实现最小图案误差的多种格局技术方法和系统
公开(公告)号：US20130094035A1
公开(公告)日：2013-04-18
申请号：US13275899
申请日：2011-10-18
申请人： Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang , Min Cao
发明人： Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang , Min Cao
IPC分类号： H04N1/60
CPC分类号： G03F1/68 , G03F1/70 , G03F7/0005 , H01L27/0207 , H01L27/1104
摘要： The present disclosure provides for many different embodiments of a multiple patterning technology method and system. An exemplary method includes receiving a pattern layout having a plurality of features; coloring each of the plurality of features one of at least two colors, thereby forming a colored pattern layout, wherein the coloring includes coloring match-sensitive features a same color; and fabricating at least two masks with the features of the colored pattern layout, wherein each mask includes features of a single color.
摘要翻译：本公开提供了多种图案化技术方法和系统的许多不同实施例。一种示例性方法包括接收具有多个特征的图案布局; 将多个特征中的每一个着色为至少两种颜色中的一种，从而形成着色图案布局，其中着色包括对相同颜色的匹配敏感特征进行着色; 以及制造具有着色图案布局的特征的至少两个掩模，其中每个掩模包括单一颜色的特征。

3. 发明授权

US07657856B1 Method and system for parallel processing of IC design layouts 失效
标题翻译： IC设计布局并行处理方法与系统
公开(公告)号：US07657856B1
公开(公告)日：2010-02-02
申请号：US11520487
申请日：2006-09-12
申请人： Mathew Koshy , Roland Ruehl , Min Cao , Li-Ling Ma , Eitan Cadouri , Tianhao Zhang
发明人： Mathew Koshy , Roland Ruehl , Min Cao , Li-Ling Ma , Eitan Cadouri , Tianhao Zhang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.
摘要翻译：公开了一种用于并行处理由IC布局处理工具执行的任务的方法和系统。在一些方法中，IC布局被划分为多个布局部分，并且一个或多个布局部分被并行处理，其中执行几何选择操作，其中用于不同布局部分的数据可以在不同处理实体之间共享。一种方法包括以下操作：选择在布局部分内执行初始选择动作的第一阶段操作; 分布式区域划分行动; 全局分区和二进制选择的分布式分区动作; 对于基于计数的选择操作的计数选择聚合; 并选择第二阶段操作来组合内部形状和界面形状的选择结果。

4. 发明申请

US20050116281A1 Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing 失效
公开(公告)号：US20050116281A1
公开(公告)日：2005-06-02
申请号：US10725234
申请日：2003-12-01
申请人： Chin-Tien Yang , Mu-Yi Lin , Yu-Wei Tseng , Min Cao , Yu-Hua Lee
发明人： Chin-Tien Yang , Mu-Yi Lin , Yu-Wei Tseng , Min Cao , Yu-Hua Lee
IPC分类号： G11C16/04 , H01L21/28 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/792 , H01L21/8238
CPC分类号： H01L27/11568 , G11C16/0458 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/7923
摘要： A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.

5. 发明授权

US06844626B2 Bond pad scheme for Cu process 有权
公开(公告)号：US06844626B2
公开(公告)日：2005-01-18
申请号：US10444229
申请日：2003-05-23
申请人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
发明人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
IPC分类号： H01L21/28 , H01L21/44 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05624 , H01L2224/05647 , H01L2224/13007 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01073 , H01L2924/01082 , H01L2924/01083 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要： A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

6. 发明授权

US06674116B1 Variable capacitor using MOS gated diode with multiple segments to limit DC current 有权
公开(公告)号：US06674116B1
公开(公告)日：2004-01-06
申请号：US09683709
申请日：2002-02-05
申请人： Min Cao
发明人： Min Cao
IPC分类号： H01L27108
CPC分类号： H01L29/94
摘要： A voltage-variable capacitor uses the channel-to-substrate junction from a gated diode formed from a metal-oxide-semiconductor transistor. The transistor gate has at least two contacts that are biased to different voltages. The gate acts as a resistor with current flowing from an upper gate contact to a lower gate contact. The gate-to-source voltage varies as a function of the position. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the gate that has gate voltages above the critical voltage has an inversion layer or conducting channel under the gate. Another portion of the gate has gate voltages below the critical voltage, and thus no channel forms. By varying either the gate voltages or the source voltage, the area of the gate that has a channel under it is varied, varying the channel-to-substrate capacitance. Separate gate arms reduce bias current.

7. 发明授权

US06384460B1 Self-aligned metal electrode structure for elevated sensors 有权
标题翻译：用于升高传感器的自对准金属电极结构
公开(公告)号：US06384460B1
公开(公告)日：2002-05-07
申请号：US09326340
申请日：1999-06-07
申请人： Jeremy A. Theil , Min Cao
发明人： Jeremy A. Theil , Min Cao
IPC分类号： H01L310376
CPC分类号： H01L27/14609 , H01L27/14603 , H01L27/14665
摘要： A self-aligned metal electrode sensor structure. The self-aligned metal electrode sensor structure includes a substrate which includes electronic circuitry. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes conductive interconnect vias which pass through the interconnect structure. A sensor is formed adjacent to the interconnect structure. The sensor includes a pixel metallization section and a doped layer electrode. The pixel metallization section is electrically connected to the interconnect via. The pixel metallization section includes an outer surface which is substantially planar. The doped layer electrode includes an inner surface adjacent to the outer surface of the pixel metallization section. The entire inner surface of the doped layer electrode is substantially planar. A transparent conductive layer is formed adjacent to the sensor. The interconnect via and the transparent conductive layer electrically connect the electronic circuitry to the sensor. An embodiment includes the outer surface of the pixel metallization section having an outer surface area which is substantially equal to an inner surface area of the inner surface of the doped layer electrode. Another embodiment includes the outer surface of the pixel metallization section having an outer surface area which is less than an inner surface area of the inner surface of the doped layer electrode.
摘要翻译：自对准金属电极传感器结构。自对准金属电极传感器结构包括包括电子电路的基板。在衬底附近形成互连结构。互连结构包括通过互连结构的导电互连通孔。邻近互连结构形成传感器。传感器包括像素金属化部分和掺杂层电极。像素金属化部分电连接到互连通孔。像素金属化部分包括基本上平面的外表面。掺杂层电极包括与像素金属化部分的外表面相邻的内表面。掺杂层电极的整个内表面基本上是平面的。在传感器附近形成透明导电层。互连通孔和透明导电层将电子电路电连接到传感器。一个实施例包括像素金属化部分的外表面，其外表面积基本上等于掺杂层电极的内表面的内表面积。另一个实施例包括像素金属化部分的外表面具有小于掺杂层电极的内表面的内表面积的外表面积。

8. 发明授权

US06315384B1 Thermal inkjet printhead and high-efficiency polycrystalline silicon resistor system for use therein 失效
标题翻译：热喷墨打印头和高效多晶硅电阻系统
公开(公告)号：US06315384B1
公开(公告)日：2001-11-13
申请号：US09604306
申请日：2000-06-26
申请人： Ravi Ramaswami , Victor Joseph , Min Cao , Theodore I. Kamins , John P. Whitlock , Anil Prem
发明人： Ravi Ramaswami , Victor Joseph , Min Cao , Theodore I. Kamins , John P. Whitlock , Anil Prem
IPC分类号： B41J205
CPC分类号： C07C323/12 , B41J2/14129 , C07C323/62 , C07D277/34 , C07D417/12
摘要： A highly-efficient thermal inkjet printhead. The printhead includes a primary layer of polycrystalline silicon (preferably doped) having at least one portion thereof which functions as an ink expulsion resistor. Positioned over and above the primary layer is a secondary layer of material having at least one section produced from a selected metal silicide compound and at least another section fabricated from undoped polycrystalline silicon. The metal silicide-containing section functions as an interconnect structure and is operatively connected to the resistor in the primary layer (which is positioned beneath the secondary layer). The undoped polycrystalline silicon section is at least partially aligned over and above the resistor. As a result, the resistor is “buried” beneath the secondary layer and the various portions thereof. This system provides improved reliability, greater dimensional simplicity, optimized electrical/thermal properties, and superior versatility.
摘要翻译：高效热敏打印头。打印头包括具有至少一部分作为墨水排出电阻器的多晶硅（优选掺杂）的主层。位于主层之上和之上的是具有由所选择的金属硅化物化合物和至少另一部分由未掺杂的多晶硅制成的至少一个部分的第二层材料。含金属硅化物的部分用作互连结构，并且可操作地连接到初级层（位于次级层下面）的电阻器。未掺杂的多晶硅部分至少部分地对准电阻器上方和上方。结果，电阻器被“掩埋”在次级层及其各个部分之下。该系统提供更高的可靠性，更大的尺寸简单性，优化的电/热性能，以及出色的通用性。

9. 发明授权

US06267471B1 High-efficiency polycrystalline silicon resistor system for use in a thermal inkjet printhead 有权
标题翻译：用于热喷墨打印头的高效多晶硅电阻系统
公开(公告)号：US06267471B1
公开(公告)日：2001-07-31
申请号：US09427512
申请日：1999-10-26
申请人： Ravi Ramaswami , Victor Joseph , Min Cao
发明人： Ravi Ramaswami , Victor Joseph , Min Cao
IPC分类号： B41J205
CPC分类号： B41J2/1645 , B41J2/14129 , B41J2/1601 , B41J2/1623 , B41J2/1628 , B41J2/1631 , B41J2/1642 , B41J2/1646
摘要： A highly-efficient thermal inkjet printhead. The printhead includes at least one doped polycrystalline silicon resistor which communicates with an external signal source using a unique interconnection system. Specifically, a primary layer of electrically conductive material (optimally a metal silicide) is connected to the resistor. An additional layer of electrically conductive material is attached to and above the primary layer. The additional layer terminates at a position which is spaced outwardly and apart from the resistor to form a gap therebetween. However, the underlying primary layer electrically links the additional layer to the resistor. Alternatively, a dielectric layer is attached to and above the primary layer, with the additional layer being secured to the dielectric layer. At least one electrically conductive contact member is provided within the dielectric layer to link the primary and additional layers. These systems provide improved reliability, greater dimensional simplicity, and optimized electrical/thermal properties.
摘要翻译：高效热敏打印头。打印头包括至少一个掺杂的多晶硅电阻器，其使用独特的互连系统与外部信号源进行通信。具体地，导电材料的主要层（最好是金属硅化物）连接到电阻器。另外一层导电材料附着到主层上方。附加层终止于与电阻器间隔开并与电阻器分开的位置，以在它们之间形成间隙。然而，底层主层将附加层电连接到电阻器。或者，电介质层附接到主层上方并且在主层上方，附加层固定到电介质层。在电介质层内提供至少一个导电接触构件以连接主层和附加层。这些系统提供改进的可靠性，更大的尺寸简单性和优化的电/热性能。

10. 发明授权

US06016011A Method and apparatus for a dual-inlaid damascene contact to sensor 有权
标题翻译：用于双嵌镶镶嵌接触传感器的方法和装置
公开(公告)号：US06016011A
公开(公告)日：2000-01-18
申请号：US300812
申请日：1999-04-27
申请人： Min Cao , Jeremy A Theil , Gary W Ray , Dietrich W Vook
发明人： Min Cao , Jeremy A Theil , Gary W Ray , Dietrich W Vook
IPC分类号： H01L21/768 , H01L23/522 , H01L31/10 , H01L31/105 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L31/1055 , H01L21/76804 , H01L21/76807 , H01L23/5226 , H01L21/7684 , H01L2924/0002
摘要： A dual-inlaid damascene contact having a polished surface for directly communicating an electrically conductive layer to a semiconductor layer. A dielectric layer is formed on the electrically conductive layer. A dual-inlaid cavity is formed by etching a via cavity and a contact cavity into the dielectric layer. A damascene contact is formed by depositing tungsten into the dual-inlaid cavity. Chemical-mechanical polishing is used to planarize and smooth a surface of the damascene contact until the surface is coplanar with the dielectric layer. A semiconductor layer is then deposited on the damascene contact. The semiconductor layer can be the node of an amorphous silicon P-I-N photodiode. Electrical interconnection between the node of the photodiode and the electrically conductive layer is accomplished without using an intermediate electrode, and the smooth damascene contact improves surface adhesion, reduces contact resistance, and provides a discrete connection to the semiconductor layer. The damascene contact may be polished to provide a light reflective surface finish for reflecting light incident on the damascene contact back into the semiconductor layer to improve the quantum efficiency of the P-I-N photodiode.
摘要翻译：具有抛光表面的双镶嵌镶嵌接触件，用于将导电层直接连接到半导体层。在导电层上形成电介质层。通过将通孔和接触腔蚀刻到电介质层中形成双嵌入腔。通过将钨沉积到双镶嵌空腔中形成镶嵌接触。化学机械抛光用于平坦化和平滑镶嵌接触面，直到表面与介电层共面。然后将半导体层沉积在镶嵌接触件上。半导体层可以是非晶硅P-I-N光电二极管的节点。在不使用中间电极的情况下实现光电二极管的节点与导电层之间的电气互连，并且光滑的镶嵌接触改善了表面粘附性，降低了接触电阻，并提供了与半导体层的离散连接。可以抛光镶嵌接触以提供光反射表面光洁度，以将入射到镶嵌触点的光反射回半导体层，以提高P-I-N光电二极管的量子效率。

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