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    • 2. 发明授权
    • Matrix operation processing device
    • 矩阵运算处理装置
    • US07085983B2
    • 2006-08-01
    • US10402623
    • 2003-03-28
    • Mitsuhiko Ohta
    • Mitsuhiko Ohta
    • H03M13/13
    • G06F17/16
    • An input data signal string I is temporarily stored in an input register, and is input to a parallel adder operating according to the instruction of a control unit. The control unit designates an address of a ROM storing a check matrix H, and obtains information about locations of “1s” in a specific column of the check matrix corresponding to a current input data bit. The ROM instructs selectors SEL1#1–SEL1#CW to select from a register reg(M) bits corresponding to rows in which the check matrix value is 1 for the specified matrix column and sends the selected values to the adder. Results of the additions and the values output from the reg(M) are selected between for input to the reg(M) through the selectors SEL2#1–SEL2#M. This process is repeated until all the input bits have been processed.
    • 输入数据信号串I临时存储在输入寄存器中,并输入到根据控制单元的指令进行操作的并行加法器。 控制单元指定存储校验矩阵H的ROM的地址,并且获取关于与当前输入数据位对应的校验矩阵的特定列中的“1s”的位置的信息。 ROM指示选择器SEL 1#1 -SEL 1 #CW从对应于指定矩阵列的校验矩阵值为1的行的寄存器reg(M)位中选择并将所选择的值发送到加法器。 在通过选择器SEL 2#1 -SEL 2 #M输入到reg(M)之间选择从reg(M)输出的添加和输出的结果。 重复该过程,直到所有输入位都被处理。