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1. 发明申请

US20100008497A1 STREAM ENCRYPTION METHOD AND ENCRYPTION SYSTEM 失效
标题翻译：流加密方法和加密系统
公开(公告)号：US20100008497A1
公开(公告)日：2010-01-14
申请号：US12492841
申请日：2009-06-26
申请人： Motomu TAKATSU
发明人： Motomu TAKATSU
IPC分类号： H04L9/20
CPC分类号： H04L9/0656 , H04L9/002
摘要： A stream encryption method encodes plaintext of N number of 1-bit input, signal sequences into L (L is N or more) bits of encrypted text using N number of pseudo random sequences and uses only one pseudo random sequence used for the encryption to decode the single corresponding plaintext. This stream encryption method comprises using the N number of pseudo random sequences to divide a L-bit encryption symbol set, averagely into two equal parts; selecting either of the two partial sets by a corresponding 1-bit plaintext sequence; and when there are one or more elements of the selected N number of partial sets forming common parts in the sets, using one of those as an encryption symbol.
摘要翻译：流加密方法使用N个伪随机序列将N个1比特输入的信号序列的明文输入L（L是N个或更多个）加密文本的比特，并且仅使用用于加密的一个伪随机序列进行解码单一对应的明文。该流加密方法包括使用N个伪随机序列将L比特加密符号集平均分成两部分; 通过相应的1位明文序列选择两个部分集合中的任一个; 并且当所选择的N个部分集合中的一个或多个元素在集合中形成公共部分时，使用其中的一个作为加密符号。

2. 发明申请

US20070210299A1 Single-photon generating device, single-photon detecting device, and optical quantum gate 有权
标题翻译：单光子发生装置，单光子检测装置和光量子门
公开(公告)号：US20070210299A1
公开(公告)日：2007-09-13
申请号：US11522421
申请日：2006-09-18
申请人： Shinichi Hirose , Motomu Takatsu , Tatsuya Usuki , Yasuhiko Arakawa
发明人： Shinichi Hirose , Motomu Takatsu , Tatsuya Usuki , Yasuhiko Arakawa
IPC分类号： H01L29/06 , H01L29/12
CPC分类号： H01L31/035281 , H01L31/02327 , H01L31/03046 , H01L33/20 , H01S5/0201 , Y02E10/50 , Y10S977/949 , Y10S977/95
摘要： A single-photon generating device is configured to have a solid substrate including abase portion, and a pillar portion which is formed on the surface side of the base portion with a localized level existent in the vicinity of the tip of the base portion. The above pillar portion is formed to have a larger cross section on the base portion side than the cross section on the tip side, so that the light generated from the localized level is reflected on the surface, propagated inside the pillar portion, and output from the back face side of the base portion.
摘要翻译：单光子产生装置被配置为具有包括基部的固体基板，并且在基部的尖端附近存在形成有位于基部的表面侧的柱部。上述柱部形成为在基部侧的截面比前端侧的截面大的截面，使得从局部水平产生的光在表面上反射，在柱部内传播，并从基部的背面侧。

3. 发明授权

US07054088B2 Information recording and reproducing apparatus and method, and signal decoding circuit for performing timing recovery 失效
公开(公告)号：US07054088B2
公开(公告)日：2006-05-30
申请号：US10273485
申请日：2002-10-18
申请人： Akihiro Yamazaki , Takao Sugawara , Motomu Takatsu , Masaru Sawada
发明人： Akihiro Yamazaki , Takao Sugawara , Motomu Takatsu , Masaru Sawada
IPC分类号： G11B5/35
CPC分类号： G11B20/10009 , G11B5/09 , G11B20/18
摘要： A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.

4. 发明授权

US06292586B1 Arithmetic unit, correlation arithmetic unit and dynamic image compression apparatus 失效
标题翻译：算术单元，相关运算单元和动态图像压缩装置
公开(公告)号：US06292586B1
公开(公告)日：2001-09-18
申请号：US09236345
申请日：1999-01-25
申请人： Susumu Kawakami , Hiroaki Okamoto , Motomu Takatsu
发明人： Susumu Kawakami , Hiroaki Okamoto , Motomu Takatsu
IPC分类号： G06K936
CPC分类号： G06F17/15
摘要： In a correlation arithmetic system adapted to detect a relative difference between two functions, an operation is simplified. This makes it possible to perform the operation with a small scale of hardware and also with great accuracy. There is adopted an operation g*h instead of the “product” in the correlation arithmetic operation. There is disclosed an arithmetic unit in which two numeral values a and b are inputted, and the two numerical values a and b are subjected to a predetermined operation process, so that a numerical value c representative of an operation result is derived. The arithmetic unit has an absolute value operation unit for evaluating an absolute value |c| of the numerical value c, and a sign operation unit for evaluating a sign “sing (c)” of the numerical value c.
摘要翻译：在适于检测两个功能之间的相对差异的相关运算系统中，简化了操作。这使得可以以小规模的硬件并且以很高的精度执行操作。在相关算术运算中采用运算g * h而不是“乘积”。公开了一种运算单元，其中输入两个数字值a和b，并且对两个数值a和b进行预定的操作处理，从而导出代表运算结果的数值c。算术单元具有用于评估绝对值| c |的绝对值运算单元的数值c的符号“sing（c）”的符号运算单元。

5. 发明授权

US5561306A Hetero-bipolar transistor having a plurality of emitters 失效
标题翻译：具有多个发射极的异质双极晶体管
公开(公告)号：US5561306A
公开(公告)日：1996-10-01
申请号：US295538
申请日：1994-08-25
申请人： Kenichi Imamura , Motomu Takatsu , Toshihiko Mori
发明人： Kenichi Imamura , Motomu Takatsu , Toshihiko Mori
IPC分类号： H01L29/73 , H01L21/331 , H01L29/02 , H01L29/08 , H01L29/205 , H01L29/737 , H01L31/0328 , H01L29/06 , H01L31/0336
CPC分类号： H01L29/0817
摘要： A hetero-bipolar transistor includes a collector layer of a first conductivity type, a base layer of a second conductivity type provided on the collector layer, a first emitter structure of the first conductivity type provided on the base layer, and a second emitter structure of the first conductivity type and provided on the base layer, wherein the first and second emitter structures are doped with respect to the base layer, with a sufficiently high impurity concentration level such that a Zener breakdown occurs at the p-n junction formed between the base layer and the first or second emitters upon application of a reverse bias voltage.
摘要翻译：异双极晶体管包括第一导电类型的集电极层，设置在集电极层上的第二导电类型的基极层，设置在基极层上的第一导电类型的第一发射极结构和第二发射极结构第一导电类型并且设置在基极层上，其中第一和第二发射极结构相对于基极层掺杂，具有足够高的杂质浓度水平，使得在形成在基极层和基极层之间的pn结处发生齐纳击穿施加反向偏置电压时的第一或第二发射极。

6. 发明授权

US5281871A Majority logic circuit 失效
标题翻译：多数逻辑电路
公开(公告)号：US5281871A
公开(公告)日：1994-01-25
申请号：US795472
申请日：1991-11-21
申请人： Toshihiko Mori , Motomu Takatsu
发明人： Toshihiko Mori , Motomu Takatsu
IPC分类号： G06F7/50 , G06F7/501 , H03K19/21 , H03K19/23 , H03K19/013
CPC分类号： G06F7/5013 , H03K19/212 , H03K19/215 , H03K19/23 , G06F2207/4822
摘要： A logic circuit including a transistor having a control electrode connected to three input terminals at which are received three respective input signals, each having, selectively, either a high or a low voltage level, and first and second electrodes, one thereof connected to a first power supply potential and the other thereof connected through a diode having N-type negative differential resistance to a second, lower power supply potential. An output terminal is connected to one of the first and second electrodes of the transistor for deriving an output signal. The load lines of the transistor are set to a first operating point for both a first condition in which all three input signals are at a low voltage level and also a second condition in which two thereof are at a high level and the third is at a low level, and to a second operating point for both a third condition in which only one of the input signals is at the high level and the remaining two input signals are at the low level and also a fourth condition in which all of the three input signals are at the high level. The current conducted by the transistor is at a first level for the first operating point and at a second level, greater than the first level, for the second operating point.
摘要翻译：一种逻辑电路，包括具有连接到三个输入端子的控制电极的晶体管，在三个输入端子处接收三个相应的输入信号，每个输入信号选择性地具有高电压或低电压电平，以及第一和第二电极，其中一个连接到第一电源电位，另一个通过具有N型负差分电阻的二极管连接到第二较低电源电位。输出端子连接到晶体管的第一和第二电极之一，用于导出输出信号。对于其中所有三个输入信号都处于低电压电平的第一状态以及其中两个处于高电平的第二状态，并且第三状态处于高电平的第二状态，晶体管的负载线被设置为第一工作点低电平的第二工作点，对于其中只有一个输入信号处于高电平且剩余的两个输入信号处于低电平的第三状态，以及其中三个输入的全部的第四条件信号处于高位。对于第二工作点，由晶体管传导的电流为第一工作点的第一电平，大于第一电平的第二电平。

7. 发明授权

US07515369B2 Information recording and reproducing apparatus and method, and signal decoding circuit for performing timing recovery 失效
标题翻译：信息记录和再现装置和方法以及用于执行定时恢复的信号解码电路
公开(公告)号：US07515369B2
公开(公告)日：2009-04-07
申请号：US11388377
申请日：2006-03-24
申请人： Takao Sugawara , Motomu Takatsu , Masaru Sawada
发明人： Takao Sugawara , Motomu Takatsu , Masaru Sawada
IPC分类号： G11B5/09
CPC分类号： G11B20/10009 , G11B5/09 , G11B20/18
摘要： A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.
摘要翻译：定时恢复单元从再现数据的头部区域检测相位偏移和频率偏移，并且最初校正它们。定时恢复单元将已经通过固定时钟将头重放信号离散的数据存储到缓冲器中。相位偏移检测器与将数据写入缓冲器的操作并行地检测与数据头区域的相位偏移。同时，频率偏移检测器与将数据写入缓冲器的操作并行地检测数据头区域的频率偏移。检测到的相位偏移的校正值和检测到的频率偏移的校正值最初被设置为数字PLL。当从缓冲器中读出数据时，在头部区域中执行频率导入和相位导入。

8. 发明授权

US07421017B2 Digital filter adaptively learning filter coefficient 失效
标题翻译：数字滤波器自适应学习滤波系数
公开(公告)号：US07421017B2
公开(公告)日：2008-09-02
申请号：US10639616
申请日：2003-08-12
申请人： Motomu Takatsu
发明人： Motomu Takatsu
IPC分类号： H03K5/159 , H04B1/10
CPC分类号： H03H21/0012 , H03H2021/0096
摘要： A linear filter feeds back an error signal generated using the output of an adaptive filter to a learning circuit. The learning circuit learns the coefficients of the adaptive filter using the error signal. The coefficients of the linear filter are determined depending on the generation method of a target signal for error minimization. In a signal interpolation type timing recovery digital filter, the coefficients of an inverse interpolation filter are determined in such a way as to minimize an error of a signal after interpolation.
摘要翻译：线性滤波器将自适应滤波器的输出产生的误差信号反馈给学习电路。学习电路使用误差信号学习自适应滤波器的系数。根据用于误差最小化的目标信号的生成方法确定线性滤波器的系数。在信号内插型定时恢复数字滤波器中，以内插后的信号的误差最小化的方式确定逆内插滤波器的系数。

9. 发明授权

US6032167A Data processing circuit adapted for use in pattern matching 失效
标题翻译：适用于模式匹配的数据处理电路
公开(公告)号：US6032167A
公开(公告)日：2000-02-29
申请号：US44973
申请日：1998-03-20
申请人： Motomu Takatsu
发明人： Motomu Takatsu
IPC分类号： G06T7/40 , G06F17/10 , G06T7/20 , G06T7/60 , G06F15/00
CPC分类号： G06T7/206
摘要： A data processing circuit adapted for use in pattern matching between two sets of multi-dimensional signal data. The data processing circuit performs integration-based conversion on data aw calculated by multiplying first multi-dimensional signal data a by a window function w, second multi-dimensional signal data b, data b.sup.2 calculated by squaring the data b, and the window function w, calculates a correlation between the first and second multi-dimensional signal data items a and b on the basis of the data aw and data b subjected to integration-based conversion, calculates a means of deviations from the square of the second multi-dimensional signal data b on the basis of the data b.sup.2 and window function subjected to integration-based conversion, and calculates a portion of the second multi-dimensional signal data b most consistent with the first multi-dimensional signal data a multiplied by the window function w. Owing to this processing, a motion vector (magnitude of movement) can be detected by carrying out a small number of arithmetic operations while hardly being affected by the variation of a signal representing the multi-dimensional signal data used for comparison. This contributes to high-precision pattern matching.
摘要翻译：一种数据处理电路，适用于两组多维信号数据之间的模式匹配。数据处理电路对通过将第一多维信号数据a乘以窗函数w，第二多维信号数据b，通过平方数据b计算出的数据b2和窗函数w来计算的数据aw执行基于积分的转换基于经过基于积分的转换的数据aw和数据b计算第一和第二多维信号数据项a和b之间的相关性，计算与第二多维信号的平方的偏差的平均值数据b基于经过基于积分的转换的数据b2和窗口函数，并且计算与第一多维信号数据a最相符的第二多维信号数据b的一部分乘以窗函数w。由于这种处理，通过执行少量的算术运算，可以检测运动矢量（运动的大小），同时几乎不受表示用于比较的多维信号数据的信号的变化的影响。这有助于高精度模式匹配。

10. 发明授权

US5426682A Sequential logic circuit having state hold circuits 失效
标题翻译：具有状态保持电路的顺序逻辑电路
公开(公告)号：US5426682A
公开(公告)日：1995-06-20
申请号：US797936
申请日：1991-11-26
申请人： Motomu Takatsu
发明人： Motomu Takatsu
IPC分类号： G06F7/00 , G05B19/07 , G11C19/28 , H03K3/36 , H03K19/21 , H03K23/54 , G11C19/00
CPC分类号： H03K3/36 , G05B19/07 , H03K19/212
摘要： A sequential logic circuit includes N state hold circuit where N is an integer. Each of the state hold circuits has a first input terminal, a second input terminal and an output terminal. The state hold circuits are cascaded via the respective first input terminals. The second input terminals of the state hold circuits receive a first clock signal. The first input terminal of one of the state hold circuits in a first stage receives a data signal. The output signal is obtained via the output terminal of one of the state hold circuits in a final stage. Each of the state hold circuits has the following truth table:______________________________________ A B Qn + 1 ______________________________________ 0 0 1 or 0 0 1 Qn 1 0 Qn 1 1 0 or 1 ______________________________________ wherein A and B designate the respective logic level signals applied to the first and second input terminals and Qn+1 designates the respective logic level of the resultant, current output signal produced at the output terminal in response to the corresponding, current logic levels input signals A and B, Qn representing that the prior logic level output signal is maintained as the current logic level output signal.
摘要翻译：顺序逻辑电路包括N状态保持电路，其中N是整数。每个状态保持电路具有第一输入端，第二输入端和输出端。状态保持电路经由各自的第一输入端子级联。状态保持电路的第二输入端接收第一时钟信号。第一级的状态保持电路之一的第一输入端接收数据信号。输出信号通过最后一级状态保持电路之一的输出端获得。每个状态保持电路具有以下真值表：-AB Qn + 1 -0 0 1或0 -0 1 Qn -1 0 Qn -1 1 0或1 - 其中A和B表示施加到第一和第二输入端和Qn + 1表示响应于对应的当前逻辑电平输入信号A和B的输出端产生的所得到的当前输出信号的相应逻辑电平，Qn表示先前的逻辑电平输出信号保持为当前逻辑电平输出信号。

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