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1. 发明专利

IL243055A Biometric identification system using pulse waveform 未知
公开(公告)号：IL243055A
公开(公告)日：2020-06-30
申请号：IL24305515
申请日：2015-12-13
申请人： PHILLIPS BRIAN KIRBY , WILSON GEOFFREY A , LIFELOC TECH INC , INTEGRATED MONITORING SYSTEMS LLC
发明人： PHILLIPS BRIAN KIRBY , WILSON GEOFFREY A
IPC分类号： A61B5/00 , A61B5/02 , A61B5/1171 , G06K9/00
摘要： A biometric identity confirmation system is based on pulse waveform data for the subject. During an initial enrollment mode, pulse waveform data for a known subject are used to generate subject characterization data for the known subject. The subject characterization data includes an exemplar created by synchronous averaging of pulse waveform data over multiple pulse cycles. A number of trigger candidates are identified for the start point of each pulse cycle. The time delay between trigger candidates is analyzed to discard false trigger candidate and identify true candidates, which are then used as the start points for each pulse cycle in synchronous averaging of the pulse waveform data. During a subsequent identity. authentication mode, pulse waveform data for a test subject are analyzed using the subject characterization data to confirm whether the identity of the test subject matches the known subject.

2. 发明专利

GB0515385D0 Glowline 未知
公开(公告)号：GB0515385D0
公开(公告)日：2005-08-31
申请号：GB0515385
申请日：2005-07-27
申请人： PHILLIPS BRIAN

3. 发明专利

GB9124161D0 VEHICLE ANTI THEFT SYSTEM 未知
公开(公告)号：GB9124161D0
公开(公告)日：1992-01-08
申请号：GB9124161
申请日：1991-11-14
申请人： TOWNSEND FRANCIS , PHILLIPS BRIAN

4. 发明专利

CA985422A DATA TERMINALS 未知
公开(公告)号：CA985422A
公开(公告)日：1976-03-09
申请号：CA156148
申请日：1972-11-10
申请人： PHILLIPS BRIAN H , YOUNG ROBERT G
发明人： PHILLIPS BRIAN H , YOUNG ROBERT G
IPC分类号： H04L7/04 , H04L25/02
摘要： A data terminal for a digital signalling system is arranged to receive incoming data transmitted in serial form and to divide the data into multi-digit signal units for supplying to a processor. Receipt of the data is controlled by a timing generator having a cycle of time slots equal to the number of digits in a signal unit. The validity of each signal unit is checked, using check bits forming part of each unit, and a check fail indication is passed to the processor if an invalid unit is detected. If the processor receives a succession of check fail indications, it initiates resynchronisation of the terminal, by resetting the timing generator. For this purpose, the terminal has a pattern recognition circuit for extracting an indication of synchronisation from the incoming data.

5. 发明专利

CA984519A MULTIPROCESSOR COMPUTER SYSTEMS 未知
公开(公告)号：CA984519A
公开(公告)日：1976-02-24
申请号：CA169509
申请日：1973-04-25
申请人： DALTON ROBIN E , PHILLIPS BRIAN H
发明人： DALTON ROBIN E , PHILLIPS BRIAN H
IPC分类号： G06F11/22 , G06F11/27 , G06F11/273 , H04Q3/545
摘要： 1434186 Multiprocessor computer systems GENERAL ELECTRIC CO Ltd 26 April 1973 [26 April 1972] 19364/72 Heading G4A A multiprocessor computer system includes a number of input/output channels 15 (Fig. 1) connected to each of a number of independent data processors 10 and fault channels 22 each connected to a monitoring interface 23 of a first processor and to a data interface of another processor so that when a fault channel is opened by a first processor its operation is monitored by the second processor. Core storage 11 is connected to all the processors 10 via leads 13. The input/output channels 15 which are connected to peripherals such as line circuits, a drum store and senders/receivers, are connected to each of the processors by fifty-four leads 14, of which 18 are reserved for two bytes of address data each with a parity bit, 18 are reserved for two bytes of output data each with a parity bit and 18 are reserved for two bytes of input data each with a parity bit. Fault channel.-The fault channel connected to the monitoring interface of processor 0 and accessible to processor 1 is shown in Fig. 2 (the connections to the data channels of the other two processors, shown in Fig. 1, are optional). Bits 0 to 5 and the parity bit of the upper byte of the address together with bits 6, 7 of the lower byte are fed to a line receiver 201 which recognizes the address allocated to the fault channel and performs a persistence check on it. If this is satisfactory it provides a clock signal on line 206 and an enabling signal on line 207 to gate 243 so that data may be fed to the processor 1. The clock signal enables the second line receiver 202 receiving bits 0 to 5 of the lower byte and the parity bit which are then fed to a fault channel address register 209 controlled by the clock signal and the " open fault channel " signal from processor 0. The register 209 includes a parity checking circuit (507, 508, Fig. 5, not shown). Output data for processor 0 is fed via line receiver 211 and gate 212 (enabled by the " open fault channel" signal) to a fault channel data register 214 controlled by the clock signal and by bit 7 of the lower address byte. When the fault channel is closed operation of the processor 0 may be monitored manually by using console keys connected via one set of AND gates (e.g. 419, Fig. 4, not shown) in data selectors 218, 221 to derive control signals on leads 219, 222. Data is fed via OR gate 225 to the processor. A console rotary switch may be operated to control multiplexer 235 so that the contents of any of the processor registers may be displayed on a console display. When the fault channel is open the signals from register 209, 214 are fed via a second set of AND gates (e.g. 418, Fig. 4, not shown) in the data selectors to the processor together with data on leads 227 from the input-output highway of processor 1 if a " data load " signal derived from bit 5 of the lower address byte exists. Data from a selected register in the processor is fed via the multiplexer 235 and a fault channel multiplexer 239 (which includes parity check circuitry) to the input data leads of processor 1 if an " interrogate " signal derived from bit 4 of the lower address byte is present. The data which is in two byte form, the second byte indicating whether the parity of the first byte is correct, may then be tested by the processor 1. Decoder.-The decoder 205 comprises a 6 input NAND gate (301, Fig. 3, not shown) connected selectively to the six address bits or their inverses. The AND gate is connected to a delay line (308) having 8 tapping points so that when the address persists for the duration of the delay the fault channel clock signal and gate data signal are derived. Software.-Tasks waiting to be examined by a process and tasks generated by a process are placed in core storage in input and output queues respectively. Any process may be run on any processor, each process having core storage assigned to it. The supervisor programme deals inter alia with the transfer of tasks, servicing requests from peripherals and handling fault conditions. Supervisor programme.-Periodically a clock 27 (Fig. 1) applies a clock signal to one of the immediate interrupt inputs of unit 25. This causes the processor running the lowest priority process to be interrupted and its register contents stored. The supervisor is then run on this processor and performs the following: (1) The interrupted process is put into its suspended state and periodic processes due to be commenced are unblocked and put into their suspended state so that they are started when a processor is avaiable. (2) Non-immediate interrupt inputs are serviced. (3) The highest priority suspended process is selected and assigned to the processor running the supervisor. The supervisor may also be initiated by a fault interrupt to run a fault routine or by a process requesting that one or more tasks that it has generated be passed to another process or by a processor requesting the supervisor to decide if it should continue running. Fault interrupt.-When a parity error is detected in a processor it inhibits its interrupt inputs and applies an " immediate fault interrupt " signal to the units 25 simultaneously with the application of an " open fault channel " signal. The interrupt signal normally results in the supervisor programme being run on the processor running the lowest priority process. If after a predetermined period the interrupt signal has not been answered the processor attempts selftesting by running a " maze programme ", a timing device being simultaneously triggered to run for a fixed period. If a fault is present the maze programme will either trap, stop or loop. If the processor traps the programme restarts and trapping will continue until the expiry of the fixed period. Similarly looping will continue until the expiry of the period. If the programme reaches its end a computed word is compared with a wired-in word and if comparison occurs the processor returns to service after generating a print-out. If the processor does not reach the end of its programme or the result is wrong the fault channel is again opened and the above process repeated. When the interrupt is answered the supervising processor enters a fault routine by applying the address of the fault channel to the address lines. It interrogates the faulty processor to see if it were running normally at the time of the fault in which case the fault is assumed to be transient and the faulty processor is put back into service after the supervising processor has taken action to prepare the abandoned process for running again or if it were running the maze programme. In the latter ease the supervisor generates a diagnosis task which is run when a processor becomes available. This processor then feeds predetermined data to the register of the faulty processor so that it executes a second (not necessarily different) maze programme. Each of the instructions of the maze programme are sequentially executed with the register content being examined at each step. When an error is detected each of the microinstructions of the instruction incorrectly performed are again executed, one at a time to find the faulty one. Next, previous faults of the processor held in core storage are compared with this fault and if it is a new fault a print out is generated. If no error is generated all the parity checking circuits of the faulty processor are tested by writing in predetermined parityincorrect data to each register in turn to see if it is detected. Roll back.-If a fault is discovered which is likely to erase information in the core stores relating to, for example, the states of the line circuits 19 (Fig. 1) roll back action is taken. The roll back routine interrogates, by a processor applying the appropriate channel and subchannel address on lines 14. Three interrogate wires Y, S, NS representing the states of particular relays in each line circuit are scanned and their information transmitted back to the processor. If Y = 0 the line is assumed to be idle. If Y = 1 signifying a call is in progress the value of the signal from the wire S is examined. If S = 0 the line is assumed to have an incoming call. If S = 1 the value of the signal from the wire NS is examined and if NS is 0 the line circuit is assumed to be in its incoming speech state. If NS = 1 it is not possible to determine exactly the state of the call from the signals on the three interrogate wires and the call is lost. The information derived from each line circuit is entered in the storage location assigned to it in core storage and the process then continues.

6. 发明申请

WO2011011079A1 IMPROVED ELECTRON BEAM STERILIZATION APPARATUS 审中-公开
标题翻译：改进的电子束灭菌装置
公开(公告)号：WO2011011079A1
公开(公告)日：2011-01-27
申请号：PCT/US2010/002071
申请日：2010-07-22
申请人： ADVANCED ELECTRON BEAMS , BUFANO, Michael, Lawrence , WALTHER, Steven, Raymond , HAYS, Peter, F. , THOMSON, William, Frederick , SOMMERSTEIN, Arthur, Wayne , FRIEDMAN, Gerald, Martin , FLETCHER, P., Michael , INTO, Stephen, Whittacker , TESTONI, Anne , EPSTEIN, Joshua , PHILLIPS, Brian
发明人： BUFANO, Michael, Lawrence , WALTHER, Steven, Raymond , HAYS, Peter, F. , THOMSON, William, Frederick , SOMMERSTEIN, Arthur, Wayne , FRIEDMAN, Gerald, Martin , FLETCHER, P., Michael , INTO, Stephen, Whittacker , TESTONI, Anne , EPSTEIN, Joshua , PHILLIPS, Brian
IPC分类号： A61L2/08 , B65B55/08 , B67C7/00
CPC分类号： A61L2/087 , B65B55/08
摘要： Improved electron beam sterilization apparatus and shielding techniques for use in are provided. A controller modulates an electron beam when sterilizing an interior to an object to ensure that adequate dose is received. Sterilization carousels are configured with input/discharge feeds to reduce the possibility of humans being exposed to dangerous levels of radiation. The system reduces the amount of shielding required to thereby lower cost of installation.
摘要翻译：提供了改进的电子束消毒装置和使用的屏蔽技术。当对物体的内部进行消毒时，控制器调制电子束，以确保接收到足够的剂量。灭菌转盘配置有输入/排放进料，以减少人体暴露于危险水平的辐射的可能性。该系统减少了所需的屏蔽量，从而降低了安装成本。

7. 发明申请

WO2009092546A2 KITCHEN EXHAUST ULTRAVIOLET SYSTEM 审中-公开
标题翻译：厨房排气超声波系统
公开(公告)号：WO2009092546A2
公开(公告)日：2009-07-30
申请号：PCT/EP2009/000260
申请日：2009-01-16
申请人： NIRO-PLAN AG , KEOGH, Alan , THOMPSON, Chris , PHILLIPS, Brian J.
发明人： KEOGH, Alan , THOMPSON, Chris , PHILLIPS, Brian J.
IPC分类号： F24C15/20
CPC分类号： F24C15/20 , A61L9/015 , A61L9/20
摘要： A reaction chamber for a use in eliminating airborne grease particles and vapor in a kitchen exhaust system includes an ultraviolet (UV) lamp, a control system configured to control the UV lamp as well as measure air flow through the reaction chamber, a first opening configured to attach the reaction chamber to an existing ventilation hood, and a second opening configured to attach the reaction chamber to an existing exhaust duct.
摘要翻译：用于消除厨房排气系统中的空气中的脂肪颗粒和蒸气的反应室包括紫外线（UV）灯，被配置为控制UV灯以及测量通过反应室的气流的控制系统，配置在第一开口将反应室附接到现有的通风罩上，以及构造成将反应室附接到现有排气管道的第二开口。

8. 发明申请

WO2005116272A3 A METHOD OF USING ENDOPHYTIC FUNGI TO DECONTAMINATE AND DECOMPOSE HUMAN AND ANIMAL WASTES 审中-公开
标题翻译：使用内生真菌去除和去除人体和动物废物的方法
公开(公告)号：WO2005116272A3
公开(公告)日：2007-03-08
申请号：PCT/US2005019240
申请日：2005-05-25
申请人： UNIV MONTANA STATE , PHILLIPS ENVIRONMENTAL PRODUCT , STROBEL GARY ALLAN , DIRKSE EMILIE , EZRA DAVID , CASTILLO UVIDELIO , PHILLIPS BRIAN
发明人： STROBEL GARY ALLAN , DIRKSE EMILIE , EZRA DAVID , CASTILLO UVIDELIO , PHILLIPS BRIAN
IPC分类号： C02F3/34 , C12N1/14 , C12S3/24
CPC分类号： C05F17/0036 , C02F3/34 , C05F3/04 , C05F17/00 , C12N1/14 , Y02A40/207 , Y02P20/145 , Y02W30/43
摘要： A method of treating human and/or animal waste products comprising contacting the waste products with an effective amount of Fusarium culmorum and Muscodor albus, together with a buffering agent and starch. The treatment process covered by the present invention can be employed in connection with pit toilets, portal a toilets, disposable waste bags, or any other environment in which the treatment of human and/or animal wastes is desired. Both the Fusarium culmorum and the Muscodor albus can be stored on infested seed grains, including, but not limited to, barley, rye, rice, wheat, mustard and grass. A method of preparing Fusarium culmorum for use in the treatment of human and/or animal wastes. An isolated culture of Fusarium culmorum. A composition comprising the same four elements used in the treatment process. A method for controlling the pH of a mixture of human liquid and sold wastes.
摘要翻译：一种治疗人和/或动物废物的方法，包括将废物与缓冲剂和淀粉一起接触废物与有效量的镰刀菌和麝香草。本发明所涉及的治疗过程可以与坑厕所，厕所门，一次性废物袋或其中期望人和/或动物废物的处理的任何其它环境有关。镰孢镰刀菌和Muscodor albus都可以储存在感染的种子谷物上，包括但不限于大麦，黑麦，稻米，小麦，芥末和草。一种制备用于治疗人和/或动物废物的镰刀菌的方法。镰刀菌分离的文化。包含在处理过程中使用的相同的四种元素的组合物。一种用于控制人体液体和废弃物的混合物的pH值的方法。

9. 发明申请

WO2004101179A3 APPARATUS AND METHOD FOR CLEANING SOILED, SURFACES WITH REDUCEDENVIRONMENTAL IMPACT 审中-公开
标题翻译：清洁土壤的设备和方法，具有减少环境影响的表面
公开(公告)号：WO2004101179A3
公开(公告)日：2005-06-02
申请号：PCT/US2004014497
申请日：2004-05-10
申请人： PHILLIPS BRIAN
发明人： PHILLIPS BRIAN
IPC分类号： A47L1/08 , A47L11/38 , B08B1/00 , B08B3/02 , B60S3/04 , A47L7/00 , A47L5/00 , A47L9/06
CPC分类号： A47L11/4044 , A47L1/08 , A47L11/38 , A47L11/4088 , B08B1/00 , B08B3/024 , B60S3/047
摘要： A method and apparatus for cleaning exterior surfaces, particularly aircraft exteriors, which method and apparatus applies cleaning solution to a soiled surface, scours the surface, squeegees the contaminated solution from the surface and evacuates it through a vacuum manifold for collection and environmentally appropriate disposal. Applicant's method and apparatus are designed principally to alleviate the problem of toxic run-off and ground water pollution as attends present-day wash-rack or bucket and brush type washing operations. Applicant's method and apparatus are also beneficial from a convenience standpoint, as an aircraft may be cleaned in any location without the necessity of removing the aircraft to a maintenance facility. Applicant's method and apparatus are also useful for other exterior surfaces, such as for cleaning skyscraper surfaces.
摘要翻译：一种用于清洁外表面，特别是飞机外部的方法和装置，该方法和设备将清洁溶液应用于污染的表面，冲洗表面，从表面上刮除污染的溶液并将其排出真空歧管以进行收集和环境适当的处置。申请人的方法和设备主要是为了缓解当今洗衣架或桶和刷式洗涤操作中的毒素流失和地下水污染的问题。从方便的角度来看，申请人的方法和装置也是有益的，因为飞机可以在任何位置进行清洁，而无需将飞机移走到维护设施。申请人的方法和装置对于其他外表面也是有用的，例如用于清洁摩天大楼的表面。

10. 发明申请

WO2004101179A2 APPARATUS AND METHOD FOR CLEANING SOILED, SURFACES WITH REDUCEDENVIRONMENTAL IMPACT 审中-公开
标题翻译：清洁土壤的设备和方法，具有减少环境影响的表面
公开(公告)号：WO2004101179A2
公开(公告)日：2004-11-25
申请号：PCT/US2004/014497
申请日：2004-05-10
申请人： PHILLIPS, Brian
发明人： PHILLIPS, Brian
IPC分类号： B08B
CPC分类号： A47L11/4044 , A47L1/08 , A47L11/38 , A47L11/4088 , B08B1/00 , B08B3/024 , B60S3/047
摘要： A method and apparatus for cleaning exterior surfaces, particularly aircraft exteriors, which method and apparatus applies cleaning solution to a soiled surface, scours the surface, squeegees the contaminated solution from the surface and evacuates it through a vacuum manifold for collection and environmentally appropriate disposal. Applicant’s method and apparatus are designed principally to alleviate the problem of toxic run-off and ground water pollution as attends present-day wash-rack or bucket and brush type washing operations. Applicant’s method and apparatus are also beneficial from a convenience standpoint, as an aircraft may be cleaned in any location without the necessity of removing the aircraft to a maintenance facility. Applicant’s method and apparatus are also useful for other exterior surfaces, such as for cleaning skyscraper surfaces.
摘要翻译：一种用于清洁外表面，特别是飞机外部的方法和装置，该方法和设备将清洁溶液应用于污染的表面，冲洗表面，从表面上刮除污染的溶液并将其排出真空歧管以进行收集和环境适当的处置。申请人的方法和设备主要是为了缓解当今洗衣架或桶和刷式洗涤操作中的毒素流失和地下水污染的问题。从方便的角度来看，申请人的方法和装置也是有益的，因为飞机可以在任何位置进行清洁，而无需将飞机移走到维护设施。申请人的方法和装置对于其他外表面也是有用的，例如用于清洁摩天大楼的表面。

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